Frequently Asked Questions: National Advanced Packaging Manufacturing Program (NAPMP) Funding Opportunity

This funding opportunity seeks applications for research and development (R&D) activities that will establish and accelerate domestic capacity for advanced packaging substrates and substrate materials.

There are two main components to this application:

Mandatory Concept Paper: Applicants will be asked to submit a concept paper. Concept papers are due on April 12, 2024.

Eligible applicants can only submit one concept plan paper under this NOFO.
No entity may be included as a subrecipient on more than two concept papers.
Concept plans received after the deadline will not be reviewed or considered.

Full Application Process: Full proposals are due July 3, 2024.

Full applications will only be accepted from applicants who were invited to submit a full application after review of their mandatory concept paper.

On March 1, 2024, CHIPS for America hosted a briefing on details of the NOFO. The presentation can be found here.

For application questions, email research [at] chips.gov (research[at]chips[dot]gov) with "2024-NIST-CHIPS-NAPMP-01 Questions" in subject.

Applicants must send an email to research [at] chips.gov (research[at]chips[dot]gov) with “2024-NIST-CHIPS-NAPMP-01 Concept Papers” in the subject line to request instructions for submitting Concept Papers. Applicants are strongly advised not to wait until the last minute to request submission instructions. The CHIPS R&D Program will respond by email with instructions for securely submitting a Concept Paper. Full applications must be submitted using Grants.gov.

Yes. Nothing in NOFO 1 prevents applicants from applying to future funding opportunities.

Please refer to section 5 for eligibility requirements. Law firms that meet these requirements may participate on submission teams.

The concept paper required forms and guidelines are in section 4.5. of the NOFO.

The eligibility rules in section 5 only refer to this NOFO and not future NOFOs.

See Section 5 on Eligibility requirements. Companies can be a lead on one proposal and be a subrecipient on two proposals.

Substrates that follow the technical description outlined in NOFO section 1.5.1 will be considered.

An applicant has the option of proposing additional performance targets that are consistent with the objectives of the NOFO. See sections 1.5.1 and 1.5.2

Table 2 on pages 14-15, defines the technical targets in the NOFO. While we do not specify the size of a "small" substrate, we encourage applicants to provide substrate solutions that assure support of a wide range of possible final substrate sizes that can be singulated from the maximum sizes listed in item #8 of the Technical targets listed on NOFO section 1.5.1.

Photonics related substrate features that are included as a feature discussed in the technical targets listed in NOFO section 1.5.1 and 1.5.2 will be considered.

The scope of “substrates” in this NOFO is limited to those related to packaging. Substrates may have functional layers on them as long as the targets in section 1.5 are met. We are unable to comment on future NOFOs at this time.

This NOFO is targeting the development of advanced packaging substrates under three broad categories: Organic-, Glass-, and Semiconductor-based. Packaging substrate materials in those categories are within the scope of this NOFO.

See sections 4.11 (FUNDING RESTRICTIONS), 4.6.1.6 (d) xi (Physical Infrastructure), and 5.3.3 (Project Management, Resources, and Budget)

Please review NOFO section 6.2.3 "Collaborations with CHIPS R&D and Other Federal Agencies".

For the purposes of this NOFO, the target areas refer to the use of a substrate material without an intermediate material (interposer) between the substrate and the chip.

For the purposes of this NOFO, the target areas refer to the use of a substrate material without an intermediate material (interposer) between the substrate and the chip. The substrate is considered the base layer that supports direct connections of chips, communication to and between chips, and power delivery. Refer to NOFO section 1.5.2 for additional details on substrate features.

Vendors selling goods and services in the ordinary course of business are not considered subrecipients for purposes of participation limits. Subrecipients are those who are designated by the lead applicant as subrecipients, included in the proposed budget, and whose activities are a continuing part of ongoing project activities and their work is tailored to specific project goals, such as research and development activities, education and workforce efforts, and other integral project efforts.

The lead applicant entity at the full application stage must have substrate prototyping capability or describe a plan to achieve that capability within 3 months of receiving an award. If current prototyping capability does not exist at the full application stage, then a plan to achieve capability, within 3 months of receiving an award should be provided. The prototype capability is not expected to perform at the final technical target level the lead applicant is addressing through R&D.

This should be consistent with the Minimum Line Width, Spacing, and Pitch technical targets outlined in section 1.5.1

Yes, terminating with copper pillars, copper pedestals or copper pads would be acceptable. Please assure you review the specification in table 2 in section 1.5.1 of the NOFO to assure termination is consistent with coplanarity at die attach (Table #2).

Yes. See Section 5 on Eligibility requirements. Companies can be a lead on one proposal and be a subrecipient on two proposals.

Yes. Please refer to NOFO section 3.1

Please refer to NOFO section 5 for application review information details.

Lead applicants will need to submit a plan for achieving the NOFO technical requirements in a phased plan. Please refer to section 11.8 for more details of what the project phases should look like.

See sections 1.5.1 and 1.5.2 on technical requirements and the inclusion of "Applicant-Defined
Target(s)"

Metal based substrates are not called out in this NOFO. Metal embedded features may be acceptable however. See NOFO Section 1.5.2 for more details.

No. TIMs described in this question are not covered in this NOFO for Substrate and substrate materials.

Proposals need to include all requirements listed in the NOFO. Team submissions may include sub-members focused on specific sub-sets of the overall NOFO requirements.

The scope of this NOFO is limited to packaging materials and substrates outlined in section 1.4.3.

Foreign organizations (e.g., for profit companies, educational institutions, and other non-profits) and foreign individuals can participate in research funded by CHIPS R&D, subject to certain limitations such as a research security review, to ensure the protection of CHIPS R&D-funded intellectual property from foreign adversaries.

To protect national security and the resiliency of supply chains, however, foreign entities of concern may not receive CHIPS R&D funds or participate in CHIPS R&D programs. Foreign entities of concern include entities owned by, controlled by, or subject to the jurisdiction or direction of the governments of China, Russia, North Korea, or Iran.

Complete definitions of foreign entity of concern and foreign country of concern are found at 15 CFR part 231.

Entities leading an application for CHIPS R&D funding must be domestic entities. Foreign organizations that are not a foreign entity of concern can participate in CHIPS R&D programs as funded subrecipients or as unfunded participants, subject to the disclosure, review, and approval processes applicable to the funding opportunity. CHIPS R&D approval processes will consider the following:

That the foreign partner’s involvement is essential to advancing program objectives, such as by offering access to unique facilities, IP, or expertise that is otherwise not readily available in the United States;

The adequacy of any agreements and protocols between the applicant and foreign partner regarding IP protection and data protection;

The partnership does not jeopardize the soundness of the project’s proposed pathway to domestic production;

As applicable, the foreign partner will comply with any necessary nondisclosure agreements, security regulations, export control laws, audit requirements, and other governing statutes, regulations, and policies;

The foreign partner is not based in a foreign country of concern as defined at 15 U.S.C. §4651(7) and implemented by the final rule entitled Preventing the Improper Use of CHIPS Act Funding, 88 FR 65600 (Sept. 25, 2023), codified at 15 C.F.R. §231.104; and
The foreign partner agrees to be subject to a research security review by CHIPS R&D, which may include a risk assessment of IP leakage, if appropriate.

An entity is owned by, controlled by, or subject to the jurisdiction or direction of a government of a foreign country listed in 10 U.S.C. 4872(d) where:

(i) The entity is:

a citizen, national, or resident of a foreign country listed in 10 U.S.C. 4872(d); and
located in a foreign country listed in 10 U.S.C. 4872(d);

(ii) The entity is organized under the laws of or has its principal place of business in a foreign country listed in 10 U.S.C. 4872(d);

(iii) 25 percent or more of the entity’s outstanding voting interest, board seats, or equity interest is held directly or indirectly by the government of a foreign country listed in 10 U.S.C. 4872(d); or

(iv) 25 percent or more of the entity’s outstanding voting interest, board seats, or equity interest is held directly or indirectly by any combination of the persons who fall within subsections (i)–(iii).

The CHIPS R&D Program Office does not impose any limitations on the citizenship of individuals employed by funding recipients. However, applicants for CHIPS R&D funding recipients must demonstrate the existence of a research security plan, which may require research security reviews of all personnel working on CHIPS R&D-funded work. The purpose of these reviews is to protect CHIPS-funded intellectual property from foreign adversaries.

A "foreign entity of concern,” as defined in the CHIPS Act² and 15 C.F.R. § 231.104, is ineligible to receive CHIPS Act funds.  However, in most instances these restrictions would not prevent an individual who is lawfully present in the United States from participating in CHIPS R&D-funded research.

Prospective applicants and subcontractors are encouraged to contact the NIST research security team (researchsecurity [at] nist.gov (researchsecurity[at]nist[dot]gov) ) for guidance on specific potential scenarios.

CHIPS R&D program participants may accept funds from foreign entities. However, federal funding recipients are required by law³ to disclose organizational affiliations and financial commitments of covered individuals—which include principal investigators and other senior and key personnel—which are reviewed for conflicts of interest during the research security review.

Performers shall also be subject to additional disclosure, review, and approval processes articulated in the applicable NOFO and any award-specific provisions negotiated with CHIPS R&D.

No. Communications with international partners consistent with the recipient’s internal international engagement policies generally do not require notifying CHIPS R&D or NIST. However, applicants and funding recipients that have concerns about specific types of outreach by foreign entities may consult the NIST research security team (researchsecurity [at] nist.gov (researchsecurity[at]nist[dot]gov))for further information.

In general, CHIPS R&D policies do not prevent funding recipients from conducting business with foreign entities of concern or from having subsidiaries in a foreign country of concern. However, CHIPS R&D funding cannot be provided to a foreign entity of concern. Additionally, all non-public information resulting (e.g., raw data or controlled unclassified information) from CHIPS R&D funded research may not be shared with a foreign entity of concern or with a subsidiary operating in a foreign country of concern.

Organizations specifically created to conduct activities on behalf of CHIPS R&D—which may include the operator of the NSTC or of the CHIPS Manufacturing USA Institute—may face additional limitations, as detailed in their funding agreements.

All award recipients will be required to provide training to individuals participating in the funded research. This training shall include guidelines for protecting project information during personal and professional travel. In general, CHIPS R&D will ensure that such operating guidelines for funding recipients are streamlined and easy to follow. Applicants and funding recipients that have questions regarding research security can contact researchsecurity [at] nist.gov (researchsecurity[at]nist[dot]gov).

NIST’s mission is to promote U.S. innovation and industrial competitiveness by advancing measurement science, standards, and technology in ways that enhance economic security and improve our quality of life.¹ In executing its responsibilities under the CHIPS Act and CHIPS and Science Act², CHIPS R&D must not only invest in research that improves U.S. economic competitiveness and the security of the domestic microelectronics supply chain but also protect that research from foreign competitors.

Unfortunately, competitor nations have aggressively sought to acquire, through licit or illicit means, U.S. intellectual property (IP), including from academic and industry research organizations. Within this environment, NIST and CHIPS R&D must protect federally funded research products and the economic and national security advantages they provide to the United States, just as companies would protect their competitive advantage.

Congress and the Administration have taken several actions to guard federally funded research and IP. For instance, National Security Policy Memorandum 33 (NSPM-33) and its subsequent Implementation Guidance require certain Federal funding recipients to establish research security programs. In response, NIST’s approach to research security seeks to balance the benefits of an open scientific research ecosystem and of international collaboration with the need to protect critical technology and IP.

NSPM-33 requires that organizations receiving more than $50 million in federal R&D funding establish their own research security programs, which must address “cyber security, foreign travel security, insider threat awareness and identification, and, as appropriate, export control training.” Federal funding agencies may establish additional requirements for these programs, including to address risks to critical and emerging technologies such as semiconductors.

In August 2023, NIST published Safeguarding International Science: Research Security Framework (NIST IR 8484) to help provide guidance on establishing a successful research security program.

Several organizations have compiled additional guidance on addressing research security, including the National Counterintelligence and Security Center’s collection of resources on Safeguarding Science, the National Science and Technology Council’s Guidance for Implementing NSPM-33, the Association of American Universities’ Science and Security Resource Document, and the National Science Foundation’s research training modules.

To support applicants for financial assistance, CHIPS R&D plans to release further information on best practices, which include (but are not limited to) establishing procedures to:

Provide research security training to relevant staff;
Identify and mitigate conflicts of interest or conflicts of commitment;
Mitigate foreign travel risks; and
Review and approve foreign requests for research collaboration, products, or services.

At present, CHIPS R&D does not require applicants to demonstrate the existence of a research security program in order to apply for or receive funding. However, applicants must provide a written plan (i.e., a research security plan) describing internal processes or procedures for addressing foreign talent recruitment programs, conflicts of commitment, conflicts of interest, research security training, and research integrity,³ as applicable.

Applicants for funding must respond to the requirements of the governing NOFO. All CHIPS R&D NOFOs will require a research security plan that demonstrates how the applicant will protect CHIPS R&D-funded research and associated data products from adversarial exfiltration.

The award recipient is responsible for meeting NIST research security requirements, including the protection of all research conducted under the research award.

Some sub-awardees maybe subject to additional research security requirements. For instance, a sub-awardee that receives more than $50 million in Federal R&D annually would be subject to additional research security requirements under NSPM-33.

To date, CHIPS R&D has not established any specific programs or set-asides to support the development of a research security program. However, limited funding may be available to implement a research security plan, subject to the objectives of the individual notice of funding opportunity (NOFO) and the approval of the relevant program director. For entities selected to receive funding, NIST may provide assistance to establish or improve research security activities consistent with NIST best practices (NIST IR 8484).

During the review of the application, the NIST Research Security and Safeguarding International Science Team will use NIST IR 8484 as the basis for reviewing and assessing research security risks. In conducting its assessment, NIST will consider factors such as the type of research to be conducted (e.g., fundamental vs. proprietary research), potential dual use applications (e.g., military and civilian), and the benefits of the research collaboration. NIST will also review available information (e.g., the Current and Pending Support Forms and Resumes or CVs) to assess whether the applicant or any covered individuals are subject to any undue foreign influence or interference by foreign strategic competitors or governments of countries that have a history of IP theft, research misconduct, or targeting U.S. technology for unauthorized transfer. If the NIST Research Security and Safeguarding International Science Team issues a risk determination that an application presents a high risk, NIST may provide the applicant, at its sole discretion, an opportunity to mitigate the assessed risk prior to CHIPS R&D making a final funding determination on the application. This research security assessment will occur separate from the CHIPS R&D evaluation based on the evaluation criteria defined within the funding opportunity.

To protect national security and the resiliency of supply chains, CHIPS for America funds may not be provided to a foreign entity of concern, such as an entity that is owned by, controlled by, or subject to the jurisdiction or direction of the governments of China, Russia, North Korea, or Iran.

Complete definitions of foreign entity of concern and foreign country of concern are found at 15 CFR part 231.

In general, restrictions on foreign entities of concern would not alone prevent an individual lawfully present in the United States from participating in CHIPS R&D-funded research. However, such individuals are subject to an individualized research security assessment. Prospective applicants and subcontractors are encouraged to contact the NIST Research Security and Safeguarding International Science Team (researchsecurity [at] nist.gov (researchsecurity[at]nist[dot]gov)) for guidance on specific potential scenarios.

As established by National Security Decision Directive (NSDD) 189:

‘Fundamental research’ means basic and applied research in science and engineering, the results of which ordinarily are published and shared broadly within the scientific community, as distinguished from proprietary research and from industrial development, design, production, and product utilization, the results of which ordinarily are restricted for proprietary or national security reasons.

Applicants for funding must respond to the requirements of the governing CHIPS R&D NOFO, which may include support for fundamental research, proprietary/restricted (non-fundamental) research, or a combination of both.

CHIPS R&D funding opportunities may ask an applicant to indicate, in their proposals, whether the applicant considers all or part of their work to be fundamental or proprietary. In instances where multiple types of research are contemplated, the applicant must describe their intent to compartmentalize fundamental and non-fundamental research activities and products. NIST and CHIPS R&D, however, reserve sole discretion to determine which elements of a proposed research project shall be considered fundamental or proprietary research. Wherever feasible, NIST and CHIPS R&D will seek to consider basic or applied research conducted on campus at a university as fundamental research.

Foreign entities of concern cannot be recipients of CHIPS funds. Publication with a foreign entity of concern shall be subject to a pre-publication review and approval by the CHIPS R&D Program Office.

No. Although fundamental research is not generally restricted by Export Administration Regulations (EAR), applicants are responsible for ensuring compliance with all export control limitations.

The definition of a “covered individual” only applies to extramural research funded by NIST. The CHIPS and Science Act defines a “covered individual” as an individual who (A) contributes in a substantive, meaningful way to the scientific development or execution of a research and development project proposed to be carried out with a research and development award from a Federal research agency; and (B) is designated as a covered individual by the Federal research agency concerned.

Those designated as covered individuals must disclose the amount, type and source of all current and pending research support, which includes both monetary and non-monetary support, and certify that the disclosure is current, accurate, and complete. All covered individuals will undergo a NIST research security review that includes consideration of, for instance, current and pending research support and potential conflicts of interest or conflicts of commitment.

NIST generally does not consider individuals who only conduct isolated tasks incidental to the research (for example, setting up equipment or performing administrative functions) or individuals who support research by executing discrete tasks as directed as covered individuals. Consistent with guidance for implementing NSPM-33, disclosures from broader classes of individuals (e.g., certain graduate students and undergraduate students) will generally be unnecessary, except when the activities of such an individual in a specific proposal rise to the level of meeting the definition of a “covered individual” under 42 U.S.C. § 6605(d)(1). For instance, NIST views authorship of a technical or scholarly publication as evidence of a truly substantial professional contribution to the research, given an author’s participation in conceiving or evolving the project design, executing one or more significant aspects of the project, or documenting the project results in a form accessible to the scientific community.

CHIPS R&D funding opportunities will require that applicants identify “covered individuals” as part of their application. Successful applicants must update the list of covered individuals as additional personnel are hired or onboarded, in accordance with the NOFO.

Subject to a research security review, foreign citizens who are designated as covered individuals may participate in CHIPS R&D-funded research as long as they do not fall within the definition of a “foreign entity of concern.”

All award recipients will be required to provide training to individuals participating in the funded research. This training shall include guidelines for protecting project information during personal and professional travel. Travel to a country of concern shall be subject to additional review.

Remote work will be addressed in the operational security element of the Awardee’s research security plan. In general, research security programs endeavor to enable flexibility for individuals while protecting research information and program data. To the extent that remote work is expected to be necessary, CHIPS R&D will work with Awardees to ensure the protection of project data. Remote work in a foreign country of concern is not allowed. Prospective applicants should contact researchsecurity [at] nist.gov (researchsecurity[at]nist[dot]gov) to discuss any specific scenarios they anticipate having to address.

An initial market assessment is critical to understanding whether a funded innovation can reach commercial scale, a key CHIPS R&D objective. Individual NOFOs may give applicants options on how to address commercialization and deployment.

Applicants should describe their business model for the funded innovation, including an initial assessment of its marketability. They should consider factors such as cost competitiveness, value proposition, and the impact of competitor products. (NAPMP M&S NOFO 4.6.1.6.d.vi)
Applicants could also identify how they will maximize the market advantages of the funded innovation, such as by reducing manufacturing costs, improving yields, or addressing performance, availability, or conformance to technical or environmental standards. (NAPMP M&S NOFO 4.6.1.6.d.vi)

An identification of future customers is desired, where known. Applicants may also identify targeted customer categories, rather than specific buyers.

Applicants should provide an overview of current or expected customer demand for the funded innovation at the volumes required for commercial viability. This includes identifying existing or potential customers, or categories of customers. (NOFO 4.6.1.6.d.vi)
Applicants should include plans for engaging with the customer ecosystem as the project advances. (NOFO 4.6.1.6.d.vi)
Applicants seeking to demonstrate community impact and support can also provide letters of commitment or interest from potential customers. (NOFO 4.6.1.6.d.vii, NOFO 4.6.1.11)

Applicants should provide sufficient information to demonstrate a realistic business model.

Describe the business model, including an initial assessment of the funded innovation’s marketability, considering factors such as cost competitiveness, value proposition, and the impact of competitor products. (NAPMP M&S NOFO 4.6.1.6.d.vi)
CVDP milestones should complement the technical milestones. For example, technical milestones should, as appropriate, inform CVDP targets and milestones such as manufacturing time, cost, performance, and projected customer demand. (NAPMP M&S NOFO 1.6.2)
Strong applications will demonstrate the potential to attract private capital, such as venture capital, potentially based on the economics of future revenue and commercial profitability. (NAPMP M&S NOFO 1.6.2)

In accordance with 15 U.S.C. §4656(g), CHIPS R&D has developed policies for the domestic production, to the extent possible, for any IP resulting from CHIPS R&D funding.

For the purposes of 15 USC 4656(g), CHIPS R&D defines production to include the manufacture, integration, assembly, testing, and packaging of semiconductor substrates and substrate materials. That includes semiconductors, materials used to manufacture semiconductors, or semiconductor manufacturing equipment developed or improved as a result of CHIPS-funded intellectual property. (NAPMP M&S NOFO 1.6.2)
CHIPS R&D does not intend to impose domestic production requirements with respect to development of software.
In the case where intellectual property relevant to the manufacture of equipment is developed with CHIPS R&D funds, domestic production requirements may apply to the production of that equipment.

CHIPS R&D aims to improve the U.S. capacity to invent, develop, prototype, manufacture, and deploy the foundational semiconductor technologies of the future. However, consistent with 15 U.S.C. 4656(g), CHIPS R&D does not require exclusive domestic production, as this goal may be served by conducting activities overseas.

Where domestic production may not be possible, applicants should identify, as practicable at the time of application, factors driving overseas production, such as (NAPMP M&S NOFO 1.6.2):

Lack of domestic production capabilities
Relative cost of domestic vs. foreign production, at relevant production volumes
Potential economic or national security benefits from having distributed production among U.S. and overseas sites
Potential risks of U.S.-based production such as market acceptance or changes to the value proposition
Other factors the applicant deems relevant to the invention's success

CHIPS R&D will favorably consider applications that demonstrate the impact of the project on regional ecosystems. Applicants can demonstrate this in a variety of ways, such as:

Showing that the project or its results will induce larger scale investments into domestic semiconductor prototyping, manufacturing, workforce development, and the creation of good jobs within a specified region (NAPMP M&S NOFO 1.9.1 and 1.9.5)
Partnerships with in-region entities focused on innovation, entrepreneurship, access to capital, and technology commercialization (NAPMP M&S NOFO 1.9.5)
Partnerships, with in-region entities, that strengthen supply chains. (NAPMP M&S NOFO 1.9.5)
Including letters of commitment or interest from entities such as community-based organizations and local officials; semiconductor and/or supply chain companies with operations or facilities in the selected or another relevant region (NAPMP M&S NOFO 1.9.5)

CHIPS for America

Frequently Asked Questions: National Advanced Packaging Manufacturing Program (NAPMP) Funding Opportunity

Application Process

Technical questions

International Engagement in CHIPS R&D Programs

CHIPS R&D Research Security and Technology Protection

Research Security Program and Research Security Plan Requirements

Foreign Entities of Concern

Fundamental Research

Research Participants and Covered Individuals

International Travel

Commercial Viability and Domestic Production (CVDP)

CHIPS for America

Frequently Asked Questions: National Advanced Packaging Manufacturing Program (NAPMP) Funding Opportunity

Application Process

What is this NOFO for?

What does the application process look like?

How can I get more information about the NOFO and application process?

How do I submit a concept paper?

If someone applies to NAPMP NOFO 1 they're still eligible to apply for future NOFOs?

Are law firms that specialize in this area allowed to participate in the current Chips R&D opportunity?

What level of detail is required for the concept paper?

If I am listed as a subrecipient on two concept papers under this NOFO, would that preclude me from participating in a future NOFO?

Can an organization be a lead on one paper while also being a Sub on one or two others?

Technical questions

What materials and substrates are eligible for this NOFO?

Can an applicant propose additional performance targets?

What are the size constrains for eligible substrates?

Do photonics related substrate features qualify for this award?

The scope of “substrates” in this NOFO seems to be narrowly defined as those related to packaging. Do you know if there will be future R&D funding opportunities for additional substrates?

Is this NOFO targeting the development of advanced material substrates?

Could you clarify the allowable and anticipated use of funds? For example, may funds be used for research facilities and equipment?

Can an applicant’s proposal for an NAPMP award include a collaborative agreement and/or technology transfer with a federal agency?

Can you clarify the difference between the TA3 silicon substrate requested and a silicon interposer that isn’t applicable?

Can you clarify the difference between the substrates requested and an interposer? Interposer and substrate are general terms often with a broad usage in the advanced packaging industry.

Who is considered a subrecipient under this NOFO?

Regarding the requirement for substrate prototyping capability or a plan for achieving that capability within 3 months of receiving an award -- is the lead entity required to have the substrate capability, or can a team member?

What is the technical target for the bonding pitch of dielets that the proposed substrate is expected to support?

Is it possible for the proposed substrate to be terminated with copper pillars for integration?

Are lead companies required to name specific subrecipients and/or partners in their proposal?

Can a company lead a proposal and also be a subrecipient of another proposal?

Does the review and grading of proposals include credit for R&D and technology transfer and commercialization?

Can a company lead a proposal if they lack their own capability to make redistribution layers so long as they have a means of delivering an RDL substrate in collaboration with a program sub, a partner or a contract manufacturer?

If a company is already producing high volume magnetics on a substrate, they put in a proposal that is focused on yield improvements, process characterization and qualification?

Are metal-based substrates eligible for funding?

Does the current NAPMP Materials and Substrates NOFO cover projects that primarily focus on thermal interface materials (TIMs) that would go between a semiconductor die and package or heatsink (i.e. TIM1, TIM1.5, TIM2)?

Sec. 1.5.2 of the NOFO mentions “Advanced substrate thermal solutions” as a topic. Could this be the primary focus of a proposal or is it supposed to be in addition to one of the core Technical Area (TA1-TA3) topics?

Does the scope of this NOFO include reticles or masks?

International Engagement in CHIPS R&D Programs

Can foreign organizations and individuals participate in CHIPS Research and Development Office (CHIPS R&D) programs?

Can foreign entities lead an application for and receive CHIPS R&D funding?

What does it mean for an entity to be owned, controlled by, or subject to the jurisdiction or direction of a government of a foreign entity of concern?

Can CHIPS R&D-funded organizations employ foreign personnel?

Can CHIPS R&D program participants accept foreign funds?

Do funding recipients have to report contact or communication with international organizations or foreign governments?

Can funding recipients do business in or have subsidiaries in a foreign country of concern?

Are CHIPS R&D program participants subject to additional disclosure and monitoring with regard to international travel?

CHIPS R&D Research Security and Technology Protection

Research Security Program and Research Security Plan Requirements

Why do the National Institute of Standards and Technology (NIST) and the CHIPS Research and Development Office (CHIPS R&D) care about research security and technology protection?

What are the key elements of a research security program?

Do entities applying for CHIPS R&D research funds need to demonstrate that they have a research security program in place before applying for a research award and/or before receiving research funding?

Will CHIPS R&D require applicants that receive less than $50M in Federal R&D funds annually to have a research security plan?

Will CHIPS R&D require all subrecipients or subcontractors participating in a CHIPS R&D research to have their own research security programs or research security plans?

Will CHIPS R&D provide funding or other resources to establish or improve a research security program or to meet other CHIPS R&D research security requirements?

How and when will NIST assess the adequacy of a research security program or research security plan?

Foreign Entities of Concern

What is a foreign entity of concern?

Can persons from a foreign country of concern participate in research?

Fundamental Research

What is fundamental research?

Will CHIPS R&D NOFOs support fundamental research, proprietary/restricted research, or a combination of both?

Can an organization publish CHIPS R&D funded work with a foreign entity of concern?

Can an organization assume that its research products are not subject to U.S. export control laws, because the organization intends to publish its research results or because NIST or CHIPS R&D has identified the research as fundamental?

Research Participants and Covered Individuals

How will the CHIPS R&D program define “covered individuals”?

When in the funding process (proposal, review, negotiation, award) will CHIPS R&D require applicants to identify covered individuals?

Can foreign citizens participate as covered individuals and work on a CHIPS R&D-funded research project?

International Travel

Are project participants subject to additional disclosure and monitoring with regard to international travel?

Can individuals work remotely outside the United States on CHIPS R&D-funded research?

Commercial Viability and Domestic Production (CVDP)

Does the CVDP plan require a comparison of the existing technology to what is currently on the market, to demonstrate commercial viability?

Should applicants consider the needs of future customers in their proposal?

What cost and revenue considerations should applicants include in their proposal?

What does “production” include? Does it apply to software or to manufacturing equipment?

What factors might CHIPS R&D consider when evaluating applications that propose non-domestic production?

How might applicants discuss how their proposal could support a regional semiconductor ecosystem?