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Displaying 176 - 200 of 759

STM patterned nanowire measurements using photolithographically defined implants in Si(100)

January 29, 2018
Author(s)
Aruna N. Ramanayaka, Hyun Soo Kim, Ke Tang, Xiqiao Wang, Richard M. Silver, Michael D. Stewart, Joshua M. Pomeroy
Using photolithographically defined implant wires for electrical connections, we demonstrate measurement of a scanning tunneling microscope (STM) patterned nanoscale electronic device on Si(100), eliminating the onerous alignment procedures and electron

Weak localization thickness measurements of embedded phosphorus delta layers in silicon produced by PH3 dosing

January 23, 2018
Author(s)
Joseph A. Hagmann, Xiqiao Wang, Pradeep N. Namboodiri, Jonathan E. Wyrick, Roy E. Murray, Michael D. Stewart, Richard M. Silver
The key building blocks for devices based on the deterministic placement of dopants in silicon are the formation of phosphorus dopant monolayers and the overgrowth of high quality crystalline Si. Lithographically defined dopant delta-layers can be formed

Analysis and Control of RRAM Overshoot Current

January 15, 2018
Author(s)
Pragya R. Shrestha, David M. Nminibapiel, Jason P. Campbell, Jason T. Ryan, Dmitry Veksler, Helmut Baumgart, Kin P. Cheung
To combat the large variability problem in RRAM,current compliance elements are commonly used to limit the inrush current during the forming operation. Regardless of the compliance implementation (1R-1R or 1T-1R), some degree of current overshoot is

Ferroelectricity in Polar Polymer-based FETs: A Hysteresis Analysis

January 15, 2018
Author(s)
Vasileia Georgiou, Dmitry Veksler, Jason Campbell, Jason Ryan, Pragya Shrestha, D. E. Ioannou, Kin P. Cheung
There is an increasing number of reports on polar polymer-based Ferroelectric Field Effect Transistors (FeFETs), where the hysteresis of the drain current - gate voltage (Id-Vg) curve is investigated as the result of the ferroelectric polarization effect

Plasma nanotexturing of silicon surfaces for photovoltaics applications: Influence of initial surface finish on the evolution of topographical and optical properties

November 27, 2017
Author(s)
Guillaume Fischer, Etienne Drahi, Martin Foldyna, Thomas Germer, Erik V. Johnson
Using a plasma to generate a surface texture with feature sizes on the order of nanometers ("nanotexturing") is a promising technique being considered for application in thin, high- efficiency crystalline silicon solar cells. This study investigates the

Towards reliable RRAM performance: macro- and microscopic analysis of operation processes

November 9, 2017
Author(s)
Gennadi Bersuker, Dmitry Veksler, David M. Nminibapiel, Pragya Shrestha, Jason Campbell, Jason Ryan, Helmut Baumgart, Maribeth Mason, Kin P. Cheung
Resistive RAM technology promises superior performance and scalability while employing well- developed fabrication processes. Conductance is strongly affected by structural changes in oxide insulators that make cell switching properties extremely sensitive

Microwave Evaluation of Electromigration Susceptibility in Advanced Interconnects

November 1, 2017
Author(s)
Yaw S. Obeng, Kin P. Cheung, Dmitry Veksler, Christopher E. Sunday
Traditional metrology has been unable to adequately address the needs of emerging integrated circuits (ICs) at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges in fabrication need to be well understood

Local field effect on charge-capture/emission dynamics

October 30, 2017
Author(s)
Kin P. Cheung, Dmitry Veksler, Jason P. Campbell
Charge-capture/emission is ubiquitous in solid state devices. Its dynamics often play critical roles in device operation and reliability. Treatment of this basic process is found in many text books and is considered well understood. As in many solid state

3D Nanometrology Based on SEM Stereophotogrammetry

September 18, 2017
Author(s)
Vipin N. Tondare, John S. Villarrubia, Andras Vladar
Three-dimensional (3D) reconstruction of a sample surface from scanning electron microscope (SEM) images taken at two perspectives has been known for decades. However, this method has not been widely used in the semiconductor industry for 3D measurements

Strain Measurement of 3D Structured Nanodevices by EBSD

August 20, 2017
Author(s)
William A. Osborn, Lawrence H. Friedman, Mark D. Vaudin
We present a new methodology to accurately measure strain magnitudes from 3D nanodevices using Electron Backscatter Diffraction (EBSD). Because the dimensions of features on these devices are smaller than the interaction volume for backscattered electrons

Interface Engineering for Nanoelectronics

August 16, 2017
Author(s)
Christina A. Hacker, Robert C. Bruce, Sujitra J. Pookpanratana
Innovation in the electronics industry is tied to interface engineering as devices increasingly incorporate new materials and shrink. Molecular layers offer a versatile means of tuning interfacial electronic, chemical, physical, and magnetic properties

Structural and electrical analysis of epitaxial 2D/3D vertical heterojunctions of monolayer MoS2 on GaN

August 4, 2017
Author(s)
Albert Davydov, Terrance P. O'Regan, Andrew A. Herzing, Dimitry Ruzmetov, Robert A. Burke, Kehao Zhang, A. Glen Birdwell, DeCarlos Taylor, E Byrd, Joshua A. Robinson, Tony G. Ivanov, M R. Neupane, S D. Walck
Integrating two-dimensional (2D) and three-dimensional (3D) semiconductors to realize vertical heterojunctions with novel electronic and optoelectronic properties is gaining interest from the device community. In this study, we utilize an approach that

Comprehensive Capacitance-Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SixGe1􀀀x and InxGa1􀀀xAs: Part II - Fits and Extraction from Experimental Data

July 21, 2017
Author(s)
Sarkar Anwar, William Vandenberghe, Gennadi Bersuker, Dmitry Veksler, Giovanni Verzellesi, Rohit Galatage, Creighton Buie, Adam Barton, Eric Vogel, Christopher Hinkle
Capacitance-voltage (C-V) measurement and analysis is highly useful for determining important information about metal-oxide-semiconductor (MOS) gate stacks. Parameters such as the equivalent oxide thickness (EOT), substrate doping density, flatband voltage

Comprehensive Capacitance-Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SixGe1􀀀x and InxGa1􀀀xAs: Part I - Model Description and Validation

July 21, 2017
Author(s)
Sarkar Anwar, William Vandenberghe, Gennadi Bersuker, Dmitry Veksler, Giovanni Verzellesi, Creighton Buie, Eric Vogel, Christopher Hinkle
High-mobility alternative channel materials to silicon are critical to the continued scaling of metal-oxidesemiconductor (MOS) devices. The analysis of capacitancevoltage (C-V) measurements on these new materials with highk gate dielectrics is a critical
Displaying 176 - 200 of 759
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