Skip to main content
U.S. flag

An official website of the United States government

Official websites use .gov
A .gov website belongs to an official government organization in the United States.

Secure .gov websites use HTTPS
A lock ( ) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.

Comprehensive Capacitance-Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SixGe1􀀀x and InxGa1􀀀xAs: Part I - Model Description and Validation

Published

Author(s)

Sarkar Anwar, William Vandenberghe, Gennadi Bersuker, Dmitry Veksler, Giovanni Verzellesi, Creighton Buie, Eric Vogel, Christopher Hinkle

Abstract

High-mobility alternative channel materials to silicon are critical to the continued scaling of metal-oxidesemiconductor (MOS) devices. The analysis of capacitancevoltage (C-V) measurements on these new materials with highk gate dielectrics is a critical technique to determine many important gate stack parameters. While there are very useful C-V analysis tools available to the community, these tools are all limited in their applicability to alternative semiconductor channel MOS gate stack analysis since they were developed for silicon. Here, we report on a new comprehensive C-V simulation and extraction tool, called CV ACE, that incorporates a wide range of semiconductors and dielectrics with the capability to implement customized gate stacks. Fermi-Dirac carrier statistics, nonparabolic bands, and quantum mechanical effects are all implemented with options to turn each of these off as the user desires. Interface state capacitance (Cit) is implemented using a common model for systems like Si and Ge. A more complex Cit model is also implemented for III-Vs that accurately captures frequency dispersion in accumulation that arises from tunneling. CV ACE enables extremely fast simulation and extraction and can accommodate measurements performed at variable temperatures and frequencies to allow for a more accurate extraction of interface state density (Dit).
Citation
IEEE Transactions on Electron Devices

Keywords

C-V Simulation, Quantum mechanical effects, Dit extraction, III-V semiconductors, thin oxides

Citation

Anwar, S. , Vandenberghe, W. , Bersuker, G. , Veksler, D. , Verzellesi, G. , Buie, C. , Vogel, E. and Hinkle, C. (2017), Comprehensive Capacitance-Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SixGe1􀀀x and InxGa1􀀀xAs: Part I - Model Description and Validation, IEEE Transactions on Electron Devices (Accessed December 3, 2024)

Issues

If you have any questions about this publication or are having problems accessing it, please contact reflib@nist.gov.

Created July 20, 2017, Updated October 12, 2021