Published: July 21, 2017
Sarkar Anwar, William Vandenberghe, Gennadi Bersuker, Dmitry Veksler, Giovanni Verzellesi, Creighton Buie, Eric Vogel, Christopher Hinkle
High-mobility alternative channel materials to silicon are critical to the continued scaling of metal-oxidesemiconductor (MOS) devices. The analysis of capacitancevoltage (C-V) measurements on these new materials with highk gate dielectrics is a critical technique to determine many important gate stack parameters. While there are very useful C-V analysis tools available to the community, these tools are all limited in their applicability to alternative semiconductor channel MOS gate stack analysis since they were developed for silicon. Here, we report on a new comprehensive C-V simulation and extraction tool, called CV ACE, that incorporates a wide range of semiconductors and dielectrics with the capability to implement customized gate stacks. Fermi-Dirac carrier statistics, nonparabolic bands, and quantum mechanical effects are all implemented with options to turn each of these off as the user desires. Interface state capacitance (Cit) is implemented using a common model for systems like Si and Ge. A more complex Cit model is also implemented for III-Vs that accurately captures frequency dispersion in accumulation that arises from tunneling. CV ACE enables extremely fast simulation and extraction and can accommodate measurements performed at variable temperatures and frequencies to allow for a more accurate extraction of interface state density (Dit).
Citation: IEEE Transactions on Electron Devices
Pub Type: Journals
C-V Simulation, Quantum mechanical effects, Dit extraction, III-V semiconductors, thin oxides
Created July 21, 2017, Updated September 01, 2017