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Electronics

Semiconductors

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Displaying 26 - 50 of 1443

A Fully Integrated, Automatically Generated DC-DC Converter Maintaining > 75% Efficiency From 398 K Down to 23 K Across Wide Load Ranges in 12-nm FinFET

January 1, 2024
Author(s)
Anhang Li, Jeongsup Lee, Prashansa Mukim, Brian Hoskins, Pragya Shrestha, David Wentzloff, David Blaauw, Dennis Sylvester, Mehdi Saligane
This paper presents a fully integrated recursive successive-approximation switched capacitor (RSC) DC-DC converter implemented using an automatic cell-based layout generation in 12 nm FinFET technology. A novel design methodology is demonstrated based on

Experimental demonstration of a robust training method for strongly defective neuromorphic hardware

December 11, 2023
Author(s)
William Borders, Advait Madhavan, Matthew Daniels, Vasileia Georgiou, Martin Lueker-Boden, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland, Brian Hoskins
Neural networks are increasing in scale and sophistication, catalyzing the need for efficient hardware. An inevitability when transferring neural networks to hardware is that non-idealities impact performance. Hardware-aware training, where non-idealities

Microstrip and Grounded CPW Calibration Kit Comparison for On-Wafer Transistor Characterization from 220 GHz to 325 GHz

November 15, 2023
Author(s)
Rob Jones, Jerome Cheron, Bryan Bosworth, Ben Jamroz, Dylan Williams, Miguel Urteaga, Ari Feldman, Peter Aaen
In this paper, we investigate the effect of two calibration errors, probe placement and capacitance per unit length, on transistor characterization from 220 GHz to 325 GHz on both a microstrip and an inverted coplanar waveguide with a via stitched ground

EDFAS FA TECHNOLOGY ROADMAP DIE-LEVEL ROADMAP COUNCIL (DLRC) POST-ISOLATION DOMAIN TECHNICAL REPORT - JAN 2023

November 10, 2023
Author(s)
Vinod Narang, Zhang Chuan, David Su, Phil Kaszuba, Steven Herschbein, Alan Street, Eckhard Langer, Martin von Haartman, Yu Zhu, Baohua Niu, Erwin Hendarto, Bryan Tracy, Jochonia Nxumalo, Rik Otte, Keana C. K. Scott
Semiconductor technologies are advancing at a rapid pace, with ongoing developments in logic and memory scaling, the introduction of new materials and transistor architectures, and the integration of advanced packaging heterogeneous technologies such as

Magnetic tunnel junction-based crossbars: improving neural network performance by reducing the impact of non-idealities

July 13, 2023
Author(s)
William Borders, Nitin Prasad, Brian Hoskins, Advait Madhavan, Matthew Daniels, Vasileia Gerogiou, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland
Increasingly higher demand in chip area and power consumption for more sophisticated artificial neural networks has catalyzed efforts to develop architectures, circuits, and devices that perform like the human brain. However, many novel device technologies

Characterization of Noise in CMOS Ring Oscillators at Cryogenic Temperatures

July 12, 2023
Author(s)
Prashansa Mukim, Pragya Shrestha, Advait Madhavan, Nitin Prasad, Jason Campbell, Forrest Brewer, Mark Stiles, Jabez J. McClelland
Allan deviation provides a means to characterize the time-dependence of noise in oscillators and potentially identify the source characteristics. Measurements on a 130nm, 7-stage ring oscillator show that the Allan deviation declines from 300K to 150K as

Measurement and Gate-Voltage Dependence of Channel and Series Resistances in Lateral Depletion-Mode b-Ga2O3 MOSFETs

June 9, 2023
Author(s)
Ory Maimon, Neil Moser, Kyle Liddy, Andrew Green, Kelson Chabak, Kin (Charles) Cheung, Sujitra Pookpanratana, Qiliang Li
Lateral depletion-mode, beta-phase gallium oxide (β-Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) with source-drain spacings of 3 µm, 8 µm, and 13 µm are studied using a modified Transfer Length Method (TLM) to obtain sheet

V-Ramp test and gate oxide screening under the "lucky" defect model

May 15, 2023
Author(s)
Kin (Charles) Cheung
The persistent (after exhaustive wafer cleaning) extrinsic breakdown distribution of thick gate oxides requires early breakdown mechanisms beyond the popular local thinning model to explain. The success of the 'Lucky" defect model in fulfilling this role

Semiconductor thermal and electrical properties decoupled by localized phonon resonances

May 10, 2023
Author(s)
Bryan Spann, Joel Weber, Matthew Brubaker, Todd E. Harvey, LINA YANG, Hossein Honarvar, Chia-Nien Tsai, Andrew Treglia, MINHYEA LEE, MAHMOUD HUSSEIN, Kris A. Bertness
Thermoelectric materials convert heat into electricity through thermally driven charge transport in solids or vice versa for cooling. To compete with conventional energy-conversion technologies, a thermoelectric material must possess the properties of both

A field-effect transistor-based room-temperature quantum current source

May 4, 2023
Author(s)
Kin (Charles) Cheung, Barry J O'Sullivan
The work provides a proof-of-concept demonstration of the room-temperature quantum current source based on nanoscale metal-oxide-semiconductor-Field-Effect-Transistor (MOSFET). Using low leakage MOSFET, the current pump achieved 1.00011 ± 0.00022 charges

Comparison of saturator designs for low volatility liquid precursor delivery

April 1, 2023
Author(s)
James E. Maslar, William A. Kimes, Vladimir B. Khromchenko, Brent Sperling, Ravindra Kanjolia
Low volatility precursors are widely utilized in chemical vapor deposition and atomic layer deposition processes. Such precursors are often delivered from one of two common saturator designs: a bubbler or a flow over vessel. Previous reports concerning

Ultrafast ID-VG Technique for Reliable Cryogenic Device Characterization

March 21, 2023
Author(s)
Pragya Shrestha, Akin Akturk, Brian Hoskins, Advait Madhavan, Jason Campbell
An in-depth understanding of the transient operation of devices at cryogenic temperatures remains experimentally elusive. However, the impact of these transients has recently become important in efforts to develop both electronics to support quantum
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