May 13, 2014
Author(s)
Richard A. Allen, Victor H. Vartanian, David T. Read, Winthrop A. Baylies
Three-dimensional stacked integrated circuit (3DS-IC) fabrication requires complex technologies such as high-aspect ratio through- silicon vias (TSVs), wafer thinning, thin wafer handling and processing, and bonding of thin wafers with complex patterned