EVALUATING METHODS OF SHIPPING THIN SILICON WAFERS FOR 3D STACKED APPLICATIONS

Published

November 7, 2012

Author(s)

Richard A. Allen, Urmi Ray, Vidhya Ramachandran, Iqbal Ali, David T. Read, Andreas Fehk¿hrer, J¿rgen Burggraf

Abstract

An experiment was performed to develop a method for choosing appropriate packaging for shipping 300 mm silicon wafers thinned to 100 µm or less for three-dimensional stacked integrated circuits (3DS-ICs). 3DS-ICs hold the promise of improved performance and/or lower power consumption for a given function by combining multiple chips into a 3D structure. However wafers thinned to 100 µm or less, which may be sourced from fabrication facilities anywhere in the world, must be collected in a single location for integration into 3D stacks. The methods evaluated were based on the procedure specified in ISO 2248:1985 “Packaging – Complete, filled transport packages – Vertical impact test by dropping.” Four types of wafer packaging systems were tested. Wafers 50 µm and 100 µm thick and drop heights of 800 mm and 1200 mm were selected. A few wafers fractured during some of the tests, mainly those wafers with significant edge defects.

Proceedings Title

International Wafer-Level Packaging Conference

Conference Dates

November 7-8, 2012

Conference Location

San Jose, CA

Pub Type

Conferences

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Local Download

Keywords

Drop tests, finite element modeling, temporary wafer bonding, three-dimensional stacked integrated circuits (3DS-IC), wafer bonding, wafer shipping

Citation

Allen, R. , Ray, U. , Ramachandran, V. , Ali, I. , Read, D. , Fehk¿hrer, A. and Burggraf, J. (2012), EVALUATING METHODS OF SHIPPING THIN SILICON WAFERS FOR 3D STACKED APPLICATIONS, International Wafer-Level Packaging Conference, San Jose, CA, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=912462 (Accessed October 14, 2025)