Metrology for 3D Integration

Published

May 13, 2014

Author(s)

Richard A. Allen, Victor H. Vartanian, David T. Read, Winthrop A. Baylies

Abstract

Three-dimensional stacked integrated circuit (3DS-IC) fabrication requires complex technologies such as high-aspect ratio through- silicon vias (TSVs), wafer thinning, thin wafer handling and processing, and bonding of thin wafers with complex patterned surfaces. Each of these new fabrication steps is associated with metrology challenges. The SEMI 3DS-IC Committee is developing a set of guides to assist the 3DS-IC community in addressing these challenges by identifying metrology solutions. In this paper we provide an overview of the metrology needs for 3DS-IC, identify metrology solutions, and provide examples from SEMI standards describing methods for characterizing the quality and strength of bonds between wafers.

Proceedings Title

ECS Trasnsaction: Moore-Than-More 2014

Volume

61

Issue

6

Conference Dates

May 12-16, 2014

Conference Location

Orlando, FL

Pub Type

Conferences

Download Paper

DOI Link

Keywords

three-dimensional stacked integrated circuits (3DS-IC), wafer bond, through-silicon via (TSV)

Citation

Allen, R. , Vartanian, V. , Read, D. and Baylies, W. (2014), Metrology for 3D Integration, ECS Trasnsaction: Moore-Than-More 2014, Orlando, FL, [online], https://doi.org/10.1149/06106.0105ecst (Accessed October 14, 2025)