Much of the Flux Quantum Electronics group’s work can be traced back to seminal work performed by Clark Hamilton and others at NIST in the 1980s. Today, with our advanced fabrication done in the NIST Boulder Microfabrication Facility we can design larger Josephson junction (JJ) circuits with higher yield and faster speeds. Additionally, by having in-house fabrication capabilities, we can proceed from design to finished chips within a few weeks, enabling fast prototyping. Shown below is a cross-sectional image, generated by NIST’s scanning electron microscope with focused ion-beam (FIB-SEM) capability, of our current wafer fabrication process. It features four niobium (Nb) metal layers (M0-M3), a bias resistor layer (RS), and self-shunted JJs. The first two metal layers are fully planarized using chemical-mechanical polishing (CMP). Traditional SFQ fabrication would include an additional junction-shunting resistor, but by using our unique process for making the junctions we can create self-shunted junctions and omit that resistor, resulting in more compact, scalable circuits.
Our JJ technology is leveraged from the decades of success of the Quantum Voltage project. The voltage standard is fabricated using the same self-shunted junction process, which allows us to fit more than a quarter of a million junctions on a single chip and therefore produce up to 10 volts output. The voltage-standard chips use Nb/NbxSi1-x/Nb JJ stacks. This niobium-doped silicon barrier is co-sputtered and thus the composition (doping) of the barrier can be modified from run to run by changing deposition powers of either the Si or Nb. To make SFQ circuits, we adjust the niobium-doping to optimize the speed and self-shunting properties of this SNS-type (superconductor-normal metal-superconductor) JJ. Doing so allows us to increase our critical current density (Jc) to 35-85 µA/µm2 using traditional optical lithography. The key result of this improvement is that it allows us to produce JJs that switch faster and circuits that operate at much higher frequencies. As a demonstration of this process, a static divider circuit was designed and fabricated which operated up to 300 GHz (shown below).
Future devices will incorporate smaller area JJs fabricated using electron-beam lithography and we expect to push Jc closer to 1000 µA/µm2. We are also exploring other materials, for example, with high kinetic inductance which will allow even more compact designs by reducing chip area taken up by large geometric inductances. We expect to produce medium-scale circuits with JJ counts in the several tens-of-thousand. In the near-term NIST designers are designing, simulating, and testing a full library of building-block digital circuits that can be tiled together to create these more complex circuits.
As discussed above, NIST is participating on IARPA’s SuperTools program. Using our expertise outlined above, we will be helping to assess the developed electronic design automation tools by providing test case designs of analog and mixed-signal circuits that we have developed and tested in-house. Also, as a fabrication center for the program, we will help the SuperTools developers of the technology computer-aided design (TCAD) to develop appropriate device models for Josephson junctions as well as the process models for the fabrication process.
Our test laboratory has also undergone recent improvements focused on being able to test larger, more complex chips at higher clock frequencies. Currently, we can test chips measuring 32 mm on a side with up to 80 input/output signals. We have focused on building a reliable, calibrated, test facility where we have advanced metrology tools for cryogenic computing applications. The C3 program has advanced from simple demonstrations of CPU components to producing complex arithmetic logic units (ALUs) and designs for and eventual CPU. NIST has acted as an inter-laboratory comparison as well as independent evaluation of the performance of the C3 participants’ designs.