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NIST researchers in the Flux Quantum Electronics (FQE) project develop cryogenic superconductive circuits and measurement techniques for advanced, energy-efficient computing, radio-frequency (RF) communications, and electrical metrology. We design, simulate, fabricate, and test niobium-based superconductive circuits for high-speed digital and mixed-signal metrology. These cryogenic circuits operate at 4 K (-269 °C) and are designed to precisely control and manipulate quantized fluxoids with state-of-the-art computational performance for their respective applications. These fluxoids are analogous to the ‘ones and zeros’ on which modern digital electronics are based.  

There are three main thrusts to our current research:

  • Quantum-accurate RF waveform synthesis in the multi-gigahertz range. This work supports NIST microwave metrology for current and future communication technologies – for example, the LTE and 5G wireless communication bands. We are building on the successes of the Quantum Voltage Project’s Josephson Arbitrary Waveform Synthesizer (JAWS) instrument and are exploring new ways to develop higher-speed AWS accurate sources for RF metrology. This project is supported through the NIST Innovations in Measurement Science program in collaboration with industry and NIST researchers the Communication Technology Laboratory
  • Big Data implies big data centers using current semiconductor-based technology, which is energy-inefficient, so the FQE project is pursuing measurement science in support of energy-efficient computing based on superconductors. Superconducting computing offers an attractive low-power alternative to semiconductor-based computing. Superconducting switches, called Josephson junctions, switch very fast, dissipate little energy per switch, and communicate signals over superconducting wires with practically no energy loss. Our team plays a key role in the precision measurements and independent verification of commercially developed, high-performance superconductive digital circuits, most recently as part of the IARPA-funded, Cryogenic Computing Complexity (C3) program. This program’s goal is to demonstrate an energy-efficient, single-flux-quantum (SFQ) based computer clocked at 10 GHz. NIST's role in this program is primarily to develop metrology for SFQ logic and cryogenic memory, complementing the circuit and computer system design expertise of the commercial partners on this program.
  • Superconducting pulse-based logic families have been around since the 1980’s and have been used to fabricate extremely fast (700 GHz) circuits that consume very little power. Nevertheless, progress of the technology has been surprisingly slow. One reason is that larger-scale integrated superconductive circuits are so complex that they cannot be designed manually and require electronic design automation (EDA) tools like those developed for the semiconductor industry. As an extension of the C3 work, another IARPA-funded program called SuperTools seeks to fill that gap by developing EDA tools for superconducting, single-flux-quantum (SFQ) electronics. These new tools will enable researchers to design, simulate, and ultimately build more complex SFQ-based digital circuits including processors intended for high-performance-computing applications. NIST’s role in this program is to evaluate the new EDA software tools using NIST’s proven SFQ circuit design and fabrication processes that include unique features not found in any other group worldwide.


Much of the Flux Quantum Electronics group’s work can be traced back to seminal work performed by Clark Hamilton and others at NIST in the 1980s. Today, with our advanced fabrication done in the NIST Boulder Microfabrication Facility we can design larger Josephson junction (JJ) circuits with higher yield and faster speeds. Additionally, by having in-house fabrication capabilities, we can proceed from design to finished chips within a few weeks, enabling fast prototyping. Shown below is a cross-sectional image, generated by NIST’s scanning electron microscope with focused ion-beam (FIB-SEM) capability, of our current wafer fabrication process. It features four niobium (Nb) metal layers (M0-M3), a bias resistor layer (RS), and self-shunted JJs. The first two metal layers are fully planarized using chemical-mechanical polishing (CMP). Traditional SFQ fabrication would include an additional junction-shunting resistor, but by using our unique process for making the junctions we can create self-shunted junctions and omit that resistor, resulting in more compact, scalable circuits.


Four-layer processing with chemical-mechanical polishing (CMP)
Scanning electron micrograph of a superconducting integrated circuit fabricated at NIST. The chip has been cross-sectioned using a focused ion-beam to show the multi-layer micro-fabrication we use to produce flux quantum electronics. The layers identified are the superconducting niobium metal layers (M0-M3) and Josephson junction (JJ), and the non‑superconducting bias resistor layer (RS).

Our JJ technology is leveraged from the decades of success of the Quantum Voltage project. The voltage standard is fabricated using the same self-shunted junction process, which allows us to fit more than a quarter of a million junctions on a single chip and therefore produce up to 10 volts output. The voltage-standard chips use Nb/NbxSi1-x/Nb JJ stacks. This niobium-doped silicon barrier is co-sputtered and thus the composition (doping) of the barrier can be modified from run to run by changing deposition powers of either the Si or Nb. To make SFQ circuits, we adjust the niobium-doping to optimize the speed and self-shunting properties of this SNS-type (superconductor-normal metal-superconductor) JJ. Doing so allows us to increase our critical current density (Jc) to 35-85 µA/µm2 using traditional optical lithography. The key result of this improvement is that it allows us to produce JJs that switch faster and circuits that operate at much higher frequencies. As a demonstration of this process, a static divider circuit was designed and fabricated which operated up to 300 GHz (shown below).


Plot of measured output frequency of a 16-stage static divider.
Plot of measured output frequency of a 16-stage static divider based on a design provided by Northrop Grumman. Each curve corresponds to a fixed input frequency. The flat sections indicate the operating margin. The top-most curve shows a maximum operating frequency of 297 GHz.

Future devices will incorporate smaller area JJs fabricated using electron-beam lithography and we expect to push Jc closer to 1000 µA/µm2. We are also exploring other materials, for example, with high kinetic inductance which will allow even more compact designs by reducing chip area taken up by large geometric inductances. We expect to produce medium-scale circuits with JJ counts in the several tens-of-thousand. In the near-term NIST designers are designing, simulating, and testing a full library of building-block digital circuits that can be tiled together to create these more complex circuits.

As discussed above, NIST is participating on IARPA’s SuperTools program. Using our expertise outlined above, we will be helping to assess the developed electronic design automation tools by providing test case designs of analog and mixed-signal circuits that we have developed and tested in-house. Also, as a fabrication center for the program, we will help the SuperTools developers of the technology computer-aided design (TCAD) to develop appropriate device models for Josephson junctions as well as the process models for the fabrication process.


Josephson junctions
A false color image showing a top-down view of a NIST-fabricated, superconducting digital circuit (8-bit shift Register). The thicker magenta lines correspond to the top wiring layer. electronic design automation (EDA) software tools are used by the circuit designer to simulate the operation of these circuits and to assist in the placement and routing of wiring.

Our test laboratory has also undergone recent improvements focused on being able to test larger, more complex chips at higher clock frequencies. Currently, we can test chips measuring 32 mm on a side with up to 80 input/output signals. We have focused on building a reliable, calibrated, test facility where we have advanced metrology tools for cryogenic computing applications. The C3 program has advanced from simple demonstrations of CPU components to producing complex arithmetic logic units (ALUs) and designs for and eventual CPU. NIST has acted as an inter-laboratory comparison as well as independent evaluation of the performance of the C3 participants’ designs.

Created January 13, 2016, Updated December 21, 2020