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Electronics

Semiconductors

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Displaying 176 - 200 of 748

3D Nanometrology Based on SEM Stereophotogrammetry

September 18, 2017
Author(s)
Vipin N. Tondare, John S. Villarrubia, Andras Vladar
Three-dimensional (3D) reconstruction of a sample surface from scanning electron microscope (SEM) images taken at two perspectives has been known for decades. However, this method has not been widely used in the semiconductor industry for 3D measurements

Strain Measurement of 3D Structured Nanodevices by EBSD

August 20, 2017
Author(s)
William A. Osborn, Lawrence H. Friedman, Mark D. Vaudin
We present a new methodology to accurately measure strain magnitudes from 3D nanodevices using Electron Backscatter Diffraction (EBSD). Because the dimensions of features on these devices are smaller than the interaction volume for backscattered electrons

Interface Engineering for Nanoelectronics

August 16, 2017
Author(s)
Christina A. Hacker, Robert C. Bruce, Sujitra J. Pookpanratana
Innovation in the electronics industry is tied to interface engineering as devices increasingly incorporate new materials and shrink. Molecular layers offer a versatile means of tuning interfacial electronic, chemical, physical, and magnetic properties

Structural and electrical analysis of epitaxial 2D/3D vertical heterojunctions of monolayer MoS2 on GaN

August 4, 2017
Author(s)
Albert Davydov, Terrance P. O'Regan, Andrew A. Herzing, Dimitry Ruzmetov, Robert A. Burke, Kehao Zhang, A. Glen Birdwell, DeCarlos Taylor, E Byrd, Joshua A. Robinson, Tony G. Ivanov, M R. Neupane, S D. Walck
Integrating two-dimensional (2D) and three-dimensional (3D) semiconductors to realize vertical heterojunctions with novel electronic and optoelectronic properties is gaining interest from the device community. In this study, we utilize an approach that

Comprehensive Capacitance-Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SixGe1􀀀x and InxGa1􀀀xAs: Part II - Fits and Extraction from Experimental Data

July 21, 2017
Author(s)
Sarkar Anwar, William Vandenberghe, Gennadi Bersuker, Dmitry Veksler, Giovanni Verzellesi, Rohit Galatage, Creighton Buie, Adam Barton, Eric Vogel, Christopher Hinkle
Capacitance-voltage (C-V) measurement and analysis is highly useful for determining important information about metal-oxide-semiconductor (MOS) gate stacks. Parameters such as the equivalent oxide thickness (EOT), substrate doping density, flatband voltage

Comprehensive Capacitance-Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SixGe1􀀀x and InxGa1􀀀xAs: Part I - Model Description and Validation

July 21, 2017
Author(s)
Sarkar Anwar, William Vandenberghe, Gennadi Bersuker, Dmitry Veksler, Giovanni Verzellesi, Creighton Buie, Eric Vogel, Christopher Hinkle
High-mobility alternative channel materials to silicon are critical to the continued scaling of metal-oxidesemiconductor (MOS) devices. The analysis of capacitancevoltage (C-V) measurements on these new materials with highk gate dielectrics is a critical

Rapid Wafer-Scale Growth of Polycrystalline 2H-MoS2 by Pulsed Metalorganic Chemical Vapor Deposition

July 12, 2017
Author(s)
Berc Kalanyan, William A. Kimes, Ryan Beams, Stephan J. Stranick, Elias J. Garratt, Irina Kalish, Albert Davydov, Ravindra Kanjolia, James E. Maslar
High volume manufacturing of devices based on transition metal dichalcogenide (TMD) ultra-thin films will require deposition techniques that are capable of reproducible wafer-scale growth with monolayer control. To date, TMD growth efforts have largely

Towards single atom devices for quantum information and metrology: weak localization in embedded phosphorus delta layers in silicon

June 29, 2017
Author(s)
Joseph A. Hagmann, Xiqiao Wang, Pradeep N. Namboodiri, Jonathan E. Wyrick, Roy E. Murray, Michael D. Stewart, Richard M. Silver, Curt A. Richter
The key building block for devices based on the deterministic placement of dopants in silicon is the formation of phosphorus dopant monolayers and the overgrowth of high quality crystalline Si. Lithographically defined dopant delta-layers can be formed

The Impact of Organic Additives On Copper Trench Microstructure

June 28, 2017
Author(s)
James B. Marro, Chukwudi A. Okoro, Yaw S. Obeng, Kathleen C. Richardson
Organic additives are typically used in the pulse electrodeposition of copper (Cu) to prevent void formation during the filling of high aspect ratio features. In this work, the role of bath chemistry as modified by organic additives was investigated for

Trion Valley Coherence in Monolayer Semiconductors

May 22, 2017
Author(s)
Kai Hao, Lixiang Xu, Wu Fengcheng, Philip Nagler, Kha Tran, Xin Ma, Tobias Korn, Allan H. MacDonald, Xiaoqin Li, Galan Moody
The emerging field of valleytronics aims to exploit the valley pseudospin of electrons residing near Bloch band extrema as an information carrier. Recent experiments demonstrating optical generation and manipulation of exciton valley coherence (the

The Lattice Spacing Variability of Intrinsic Float-Zone Silicon

May 11, 2017
Author(s)
Ernest G. Kessler Jr., Csilla Szabo-Foster, James Cline, Albert Henins, Lawrence T. Hudson, Marcus Mendenhall, Mark D. Vaudin
Precision lattice spacing comparison measurements at the National Institute of Standards and Technology (NIST) provide traceability of x-ray wavelength and powder diffraction standards to the international system of units (SI). Here we both summarize and

The dependence of electrical performance on structural organization in low mobility polymer field effect transistors

April 16, 2017
Author(s)
Emily G. Bittle, Hyun W. Ro, Chad R. Snyder, Sebastian Engmann, Regis J. Kline, Oana Jurchescu, Dean M. DeLongchamp, David J. Gundlach
Polymer semiconductors are contenders for use in printed, flexible electronics. Though organic electronic materials have been studied for many years, the physics of charge transport is still under investigation. This is in part due to the large variability

Cryogenic pulsed I-V measurements on homo- and heterojunction III-V TFETs

April 1, 2017
Author(s)
Quentin Smets, Jihong Kim, Jason Campbell, David M. Nminibapiel, Dmitry Veksler, Pragya Shrestha, Rahul Pandey, Anne S. Verhulst, Eddy Simoens, David J. Gundlach, Curt A. Richter, Kin P. Cheung, Suman Suman, Anda Mocuta, Nadine Collaert, Aaron Thean, Marc Heyns
Most experimental reports of tunneling field-effect transistors show defect-related performance degradation. Charging of oxide traps causes Fermi level pinning, and Shockley-Read-Hall (SRH)/trap-assisted tunneling (TAT) generation cause unwanted leakage
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