CHIPS R&D Digital Twin Technical Standards Workshop

You can find the Workshop Summary Report here. 

The CHIPS Research and Development (R&D) Office held a series of events to obtain public input from stakeholders on standards priorities for the semiconductor sector. At the inaugural CHIPS R&D Standards Summit in Washington, DC in September 2023, private sector thought leaders provided broad input on strategic priorities as detailed in the Summary Report. Some of the recommendations included exploring standards opportunities within specific technical priority areas and metrics to strengthen the link between research and standards. A series of follow-on technical workshops were held in December 2023, April 2024, and June 2024 to explore these recommendations from the Summit. Each workshop was organized by a diverse planning committee and featured a mix of presentations from experts in the field followed by interactive breakout discussion sessions. These events assembled technical experts from the semiconductor industry, academia, standards setting/development organizations (SSOs /SDOs), industry alliances, and government to discuss opportunities in the semiconductor community for the following areas:

1. Chiplets Interfaces Technical Standards                                                  December 12-13, 2023
2. Digital Twin Technical Standards                                                               December 14-15, 2023
3. Semiconductor Supply Chain Trust and Assurance Data Standards              April 2-3, 2024
4. Digital Twin Data Interoperability Standards                                                        April 4-5, 2024
5. Standardization Readiness Level                                                                                June 4-5, 2024

In the first two workshops in December 2023, participants discussed the potential for chiplet-based architectures and digital twin applications, respectively, to drive progress in the semiconductor industry and the role of standards for enabling innovation. Two follow-on workshops were held in April 2024 to identify the data standards needed to assure secure electronics supply chains and to further refine the priorities for digital twin data interoperability standards, respectively. In the fifth workshop, participants discussed whether well-defined standardization readiness level metrics, tailored for use in semiconductor standards development, could serve as a crucial guide for determining if and when research outcomes should be integrated into voluntary industry standards activities. More complete event descriptions can be found on the web pages for each workshop (links provided above).

The first four workshops focused on identifying community standards opportunities in technical priority areas identified by industry during the Summit. During each workshop, participants debated, consolidated, and used interactive polling to upvote the top standards ideas for the technical focus area being discussed. The top standards needs identified by participants during each workshop are listed below.

1.Chiplets Interfaces Standards Needs:

• System optimization (modeling, simulation, and testing standards)
• Security and traceability testing standards
• General testing and verification standards (outside of security)
• Interconnection protocol 
• Chiplet abstraction (e.g., process design kits (PDKs))

2. Digital Twin for Semiconductor Manufacturing Standards Needs:

• Interoperability (data models, digital twin interfaces, digital twins communicating with other digital twins)
• Digital twin taxonomy and definitions
• Security (data provenance, traceability, digital thread)
• Testing, validation, verification (reliability testing, uncertainty verification, benchmark testing, methodologies, creation of new metrics)
• Existing standards (database of standards, analysis of standards, governance)

3. Semiconductor Supply Chain Trust and Assurance Data Standards Needs:

• Semantic definitions, assets, and standards to support traceability and provenance of semiconductor materials and data, both in the physical and virtual space, across the entire product lifecycle.
• Develop an updated, more accessible, parameterized database of existing supply chain trust and assurance data standards (e.g., taxonomy, matrix, graph, analytic tool, etc.).
• More precise, scalable, and diverse methods and identifiers for traceability (this enables more credible provenance).
• Develop an umbrella/macro-level framework for aligning standardization activities across the semiconductor supply chain.
• Standardized format/architecture/security/automated key management/proof of authority/ identify verification and management for sustainment chains, distributed ledgers

4. Digital Twin Data Interoperability Standards Needs:

• Develop a shared hierarchical relationship of digital twin systems (mesh/context and layers of detail/granularity/resolution). Develop a roadmap for standards [may use the International Roadmap for Devices and Systems (IRDS), smart manufacturing section, as a starting point].
• New and/or standard methods for communicating accuracy difference/uncertainty between the real event (i.e., actual metrology) and the predictions from the digital twin (i.e., virtual metrology). 
• Clear definition of context-specific interfaces. 
• Global, automated, cryptographic identifiers and key management infrastructure (to ensure seamless, zero trust cybersecurity for digital twins across domains).
• Standard for tracing/attributing changes to data as it travels through the supply chain.

5. Standardization Readiness Level Framework and Scale Recommendations:

• A consensus framework would help inform standards strategies for emerging semiconductor technologies and should be further developed.
• An existing, notional NIST standardization readiness framework—with elements of technology, market, and community—provides a good baseline of considerations that are also applicable to semiconductor standards development.
• The NIST framework should be expanded to include best-practices for community-building, including highlighting the role of incubators and accelerators in providing opportunities to collaborate on pre-standardization activities. 
• A simple-to-use standardization readiness level scale would be useful for understanding and communicating the standards process and lifecycle.

Workshop participants across all five workshops also made broad recommendations for the semiconductor standards community. A summary of some of the key recommendations from the participants are provided below:

• An alliance of standards setting and development organizations would help to guide the development of standards for the semiconductor industry. Some of the proposed activities of the alliance could include:
  • Developing and maintaining a semiconductor standards roadmap
  • Convening industry to identify priorities, inform roadmaps, form working groups, etc. 
  • Developing and maintaining standards registries
• A critical assessment of existing standards across all major topic areas of the first four workshops (i.e., chiplets, digital twins, digital twin data interoperability, supply chain trust and assurance data) is needed to avoid duplication or siloed standards efforts. This would be assisted by having standards registries.
• Standards education must be emphasized at all levels in the semiconductor supply chain and should serve broad audiences (e.g., technical experts, fab operators, workforce developers, finance specialists, executives, etc.)
• The CHIPS R&D programs and institutes should consider how to support semiconductor standards development activities.

More information about each of these standards needs, recommendations, and other key findings from each workshop will be detailed in forthcoming reports that will be posted on each workshop event page.