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CHIPS R&D Chiplets Interfaces Technical Standards Workshop

CHIPS R&D Chiplets Interfaces Technical Standards workshop
Credit: Andrew Kim

The CHIPS Research and Development Office’s Chiplets Interfaces Technical Standards Workshop will be held as a hybrid in-person and virtual event from 8:30 a.m. to 5:30 p.m. Eastern Time December 12, 2023, and 8:30 am to 12:30 pm December 13, 2023.  This event will bring together technical experts from industry, academia, standards setting organizations, and industry alliances, domestic and abroad, to identify community priorities for specific standards efforts.

The workshop will be a place to foster collaboration, coordination, and innovation within the semiconductor industry's standards community. Participants will discuss the potential for chiplet-based architectures to drive progress in the semiconductor and microelectronics industry and the role of technical standards for physical and logical interfaces in enabling innovation. Factors to be considered in identifying standards priorities include potential for broad impact, feasibility for accelerated development, and suitability for various standards development channels, including through alliances, incubators and accelerators, and standards setting organizations.

This one and one-half day hybrid event provides an opportunity to network and exchange ideas with thought leaders across the sector. The morning of Day One features plenary and panel sessions with exemplary keynote and guest speakers. Breakout sessions the afternoon of Day One and the morning of Day Two provide an opportunity for participants to collaborate and discuss key topics that will shape future chiplets standards activities. Key findings will be published in a post-workshop report and will inform standards planning efforts across the semiconductor innovation ecosystem and within the CHIPS R&D Office.

We encourage interested stakeholders, industry representatives, and standards setting organizations to participate actively in this pivotal event. We also invite international attendees, as fostering global collaboration and enriching the discussions on advancing semiconductor standards and innovation is paramount to success. Join us at the CHIPS R&D Chiplets Interfaces Technical Standards Workshop as we collaboratively shape the future of semiconductor and microelectronics standards, foster innovation, and advance the industry as a whole. Finally, we note that a related workshop focused on digital twin technical standards will be held Dec. 14-15 at the same site. Information regarding this related workshop (separate registration required) can be found on the website for those who may want to attend both events.


DAY 1: December 12, 2023/ 8:30 AM - 5:35 PM




7:30 –8:30 am



8:30 –8:35 am

Introduction to the workshop / review agenda / logistics

Jan Obrzut (CHIPS R&D)

8:35 –8:50 am

Keynote 1: Chiplets – The Centerpiece of Advanced Packaging

Subramanian Iyer (Director, National Advanced Packaging Manufacturing Program, CHIPS R&D) (Virtual)

8:50 – 9:05 am

Keynote 2: Importance of Technical Standards in the Semiconductor Ecosystem

Kathleen Kingscott (IBM Research)

9:05 – 10:30 am

Panel 1: Tutorial on chiplets interface standards


Lalitha Immaneni (Intel) Moderator


  1. Die-to-die parallel interfaces for the emerging chiplet market
  2. Building the open chiplet economy


  1. A standard for chiplet interconnect test and repair
  2. The realities of physical limits and prospects for 2 / 2.5 -D and 3-D interconnects
  1. Elad Alon (Blue Cheeta Analog(Virtual)
  2. Bapi Vinnakota (Open Compute Project)
  3. Sreejit Chakravarty (Ampere)
  4. Dev Gupta (APSTL) (Virtual)


10:30 –10:45 am



10:45 –11:45 am

Breakout Session 1: Discuss and prioritize ideas related to panel 1


Led by SIDEM and Corner Alliance facilitators

11:45 –12:00 pm

Report Out from Breakout Session 1

Workshop participants and facilitators

12:00 –1:15 pm




1:15 –2:15pm

Panel 2: State-of-the-art in chiplets interfaces         

Gretchen Greene (NIST) Moderator


  1. Die-to-die parallel interfaces for the emerging chiplet market
  2. Packaging and chiplets: Needs for standards and EDA evolution
  3. Advanced packaging, assembly, test, and failure analysis
  4. Experience and ideas for enhancing the chiplet ecosystem, die-to-die interfaces, packaging supply chain limitations, business model challenges, and optical packaging requirements
  5. Chiplets interfaces challenges in packaging
  1. Andreas Olofsson (Zero ASIC)


  1. Lalitha Immaneni (Intel)


  1. Yan Li (Samsung)


  1. Chen Sun (Ayar Labs) (Virtual)



  1. Jeff Rearick (AMD) (Virtual)

2:15 –3:15pm

Breakout Session 2: Discuss and prioritize ideas related to panel 2

Led by SIDEM and Corner Alliance facilitators

3:15 –3:30pm

Report Out from Breakout Session 2

Workshop participants and facilitators

3:30 –4:00pm



4:00 –4:45 pm

Panel 3: Current state of research in chiplets

Veruska Malave (NIST) Moderator


  1. Photonics packaging


  1. Modeling challenges of systems co-design


  1. High-level approaches to hardware and embedded security
  2. The tradeoffs between performance and resources in natural and engineered systems
  1. Peter O’Brien (Tyndall Institute) (Virtual)
  2. Ganesh Subbarayan (Purdue University)
  3. Ramesh Karri (NYU)


  1. Pamela Abshire (U. Md)


4:45 –5:15 pm

Breakout Session 3: Prioritize ideas from panels 1, panel 2, and panel 3

Led by SIDEM and Corner Alliance facilitators

5:15 – 5:35pm

Report Out from Breakout Session 3

Workshop participants and facilitators





DAY 2: December 13, 2023/ 8:30 AM – 12:00 PM

8:30 –9:30 am

PANEL 4: Summary Discussion/Takeaways from

Day 1

Andreas Olofsson (Zero Asic) Moderator



  • What are the technical standards gaps?
  • What information is needed to address the gaps?
  • How do we prioritize which standards to work on?
  • Who can help with the standards development effort?
  • Which SSO's should be working on these issues?


  1. Bapi Vinnakota (Open Compute Project)
  2. Lalitha Immaneni (Intel)
  3. Chen Sun (Aylar Labs) (Virtual)
  4. Melissa Grupen-Shemansky (SEMI)
  5. Debendra Das Sharma (UCIe Consortium Standards) (Virtual)

9:30 – 10:30 am

Breakout Session 4: Discuss and prioritize ideas related to panel 4

Led by SIDEM and Corner Alliance facilitators

10:30 –11:00 am



11:00 –12:00pm

Report Out from Breakout Session 4 and consolidation of priorities

Workshop participants and facilitators

12:00 –12:30 pm

Discuss next steps

Jan Obrzut & Yaw Obeng (CHIPS R&D Office)

12:30 pm

End of workshop - adjourn



*Visitor Access Requirement:

For Non-US Citizens:  Please have your valid passport for photo identification.

For US Permanent Residents: Please have your green card for photo identification.

For US Citizens: Please have your state-issued driver's license. Regarding Real-ID requirements, all states are in compliance or have an extension through May 2025.

NIST/NCCoE also accepts other forms of federally issued identification in lieu of a state-issued driver's license, such as a valid passport, passport card, DOD's Common Access Card (CAC), Veterans ID, Federal Agency HSPD-12 IDs, and Military Dependents ID.

Created October 17, 2023, Updated December 12, 2023