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Search Publications

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Displaying 51076 - 51100 of 73697

Chaos

December 31, 1998
Author(s)
Richard L. Kautz

Dopant Characterization Round-Robin Study Performed on Two-Dimensional Test Structures Fabricated at Texas Instruments

December 31, 1998
Author(s)
J. Vahakangas, Markku Lahti, M C. Chang, H Edward, C F. Machala, R S. Martin, V Zavyalov, J S. McMurray, C. C. Williams, P DeWolf, Vandevorst, D. Venables, S S. Neogi, D L. Ottaviani, Joseph Kopanski, J F. Machiando, Brian G. Rennex, J N. Nxulamo, Y Li, D J. Thomson
The lack of a two-dimensional (2D) dopant standard, and hence, a priori knowledge of dopant distribution makes it impossible to unambiguously judge accuracy of any experimental or theoretical effort to characterize silicon doping in two dimensions

Extraction of Sheet-Resistance from Four-Terminal Sheet Resistors in Monocrystalline Films Having Non-Planar Geometries

December 31, 1998
Author(s)
Michael W. Cresswell, Nadine Guillaume, Richard A. Allen, William F. Guthrie, Rathindra Ghoshtagore, James C. OwenI II, Z. Osborne, N. Sullivan, Loren W. Linholm
This paper describes methods for the extraction of sheet resistance from V/I measurements made on four-terminal sheet resistors incorporated into electrical linewidth test structures patterned with non-planar geometries in monocrystalline silicon-on

Failure Dynamics of the IGBT During Turn-Off for Unclamped Inductive Loading Conditions

December 31, 1998
Author(s)
Chien-Chung Shen, Allen R. Hefner Jr., David W. Berning, J B. Bernstein
The internal failure dynamics of the Insulated Gate Bipolar Transistor (IBGT) for unclamped inductive switching (UIS) conditions are studied using simulations and measurements. The UIS measurements are made using a unique, automated nondestructive Revers

MEMS-Based Test Structures for IC Technology

December 31, 1998
Author(s)
S. A. Smee, Michael Gaitan, Yogendra K. Joshi, David L. Blackburn
As Integrated Circuit (IC) device sizes shrink, intrinsic and thermo-mechanical stress in interconnects is an ever increasing reliability concern. Increasing device density leads to more interconnect layers and hence, greater probability of stress related

Reliability Characterization of Ultra-Thin Film Dielectrics

December 31, 1998
Author(s)
John S. Suehle
The reliability of gate oxides is becoming a critical concern as oxide thickness is scaled below 4 mm in advanced CMOS technologies. Traditional reliability characterization techniques must be modified for very thin gate oxides and soft breakdown. As
Displaying 51076 - 51100 of 73697
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