Dr. Daniel Josell joined NIST as a National Research Council postdoctoral researcher in the Metallurgy Division of the Materials Science and Engineering Laboratory in 1992. He became a permanent staff member in 1994. He has been Deputy Chief of the Metallurgy Division of NIST's Materials Science and Engineering Laboratory as well as Leader of the Division's Thin Film and Nanostructure Processing Group. He has also been a Technology Analyst in NIST's Program Office. He is author of more than 120 technical papers and two US patents.
He has received the:
Over the last decade his research has focused on advanced electrochemical deposition processes for void-free, defect-free filling of recessed features, including for fabrication of interconnects for microelectronics:
He has also examined the mechanical and thermal transport properties of multilayered materials, the thermodynamics of interfaces and the stability of nanoscale materials and structures.
Results for some efforts are given below (full details can be found in the publications).
Superfill for interconnect fabrication: Superconformal deposition has enabled damascene copper interconnects in microelectronics. Models based on the Curvature Enhanced Accelerator Coverage (CEAC) mechanism capture all aspects of superfill: incubation period of conformal growth, accelerating bottom-up filling, and overfill bump formation
CEAC-derived superconformal deposition is generic, as shown by silver superfill.
Filling of larger features by S-NDR mechanism: Electrolytes that allow passivation of a portion of the surface while another portion is actively depositing can yield bottom-up deposition in patterned features. The mechanism underlies copper filling of Through Silicon Vias (TSV) for wafer stacking applications in microelectronics. S-NDR models explain this phenomenon, having provided quantitative prediction of copper, nickel, cobalt and gold feature filling, including two quite different geometries from the same mechanism:
S-NDR models predict bottom-up Cu deposition in micrometer size TSV
as well as much larger, millimeter size vias
and Through-Hole vias for printed circuit boards
They also explain activation of the feature bottom as well as a portion of the sidewalls observed with systems exhibiting substantial suppressor incorporation, including cobalt
Bottom-up gold deposition for diffraction gratings: A newly developed process yields void-free, defect-free bottom-up gold deposition in tall and high aspect ratio features. In its third year, the effort is now receiving support from NIST's Associate Director for Laboratory Program through the Technology Maturation Accelerator Program. Collaborations, in place and being developed, focus on transferring NIST's Au filling technology for fabrication of diffraction gratings to be used in imaging applications.
Filling of taller features requires a shift to more positive potentials that yield an increasingly long period of passive deposition prior to bottom-up filling.
The process can be made self-passivating, filling automatically halting at a controllable distance from the field.
Void-free filling of trenches up to 210 micrometers deep and with aspect ratio (height/width) up to 30 has been detailed. An interesting microstructure and texture suggesting recrystallization from the sidewalls is observed by electron backscatter diffraction.
Void free, bottom-up gold filling has also been demonstrated in trenches of aspect ratio 56 and on fully patterned 4 inch silicon wafers.
3D microstructured photovoltaics: Photovoltaic devices with interdigitated back contacts are fabricated using a single lithography step followed by (non)selective deposition of p-type and n-type materials.
Optical response of structures with systematically varied geometries (e.g., electrode height, width and pitch) can be used to characterize the properties of materials and interfaces in structured photovoltaic devices.
The role of surface passivation in eliminating defects that reduce define performance is also examined, using both standard i-V response under illumination as well as spatial mapping
Exploding wire experiments and modeling - studies of alloy melting: Surface morphology of rapidly melted TiNb alloys near critical features of the melting plateau reflect solidus and liquid temperatures that are measured through combination of pyrometry and polarimetry.
The impact of grain size on local melting rate, and thus solute diffusion, is captured in rescaled data.
Thermal transport in multilayered films: Measurements using the "Mirage" technique enable measurement of thermal transport both in-plane and normal to the surface of thin film samples.These results showed the impact of decreasing the nanometer-scale bilayer thickness in Ti/Al multilayers of total thickness 3 micrometers.
Interpretation of these and other properties of multilayer thin films must necessarily consider their microstructure, including interfacial mixing as evident in TEM images and associated composition maps of some of the Ti/Al multilayers.