U.S. flag

An official website of the United States government

Official websites use .gov
A .gov website belongs to an official government organization in the United States.

Secure .gov websites use HTTPS
A lock ( ) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.

Electronics

Search Publications

Search Title, Abstract, Conference, Citation, Keyword or Author
  • Published Date
Displaying 1 - 25 of 1312

Metrics and Methodology for Hardware Security Constructs

June 5, 2025
Author(s)
Sanjay Rekhi, Kostas Amberiadis, Abir Ahsan Akib, Ankur Srivastava
Although hardware is commonly believed to be security-resilient, it is often susceptible to vulnerabilities arising from design and implementation flaws. These flaws have the potential to jeopardize not only the hardware's security, but also its operations

280-GHz aluminum MKID arrays for the Fred Young Submillimeter Telescope

May 29, 2025
Author(s)
Anna Vaskuri, Jordan Wheeler, Jason Austermann, Michael Vissers, James Beall, James R. Burgoyne, Victoria Butler, Scott Chapman, Steve K. Choi, Abigail Crites, Cody J. Duell, Rodrigo Freundt, Anthony Huber, Zachary Huber, Johannes Hubmayr, Jozsef Imrek, Ben Keller, Lawrence Lin, Alicia Middleton, Michael D. Niemack, Thomas Nikola, Douglas Scott, Adrian Sinclair, Ema Smith, Gordon Stacey, Joel Ullom, Jeffrey Van Lanen, Eve Vavagiakis, Samantha Walker, Bugao Zou
First light observations of the 280 GHz instrument module of the Fred Young Submillimeter Telescope (FYST) in the CCAT Collaboration are expected in 2026. The focal plane of this module will consist of three superconducting microwave kinetic inductance

Impact-Ionization-Based High-Endurance One-Transistor Bulk CMOS Cryogenic Memory

March 31, 2025
Author(s)
Pragya Shrestha, Alexander Zaslavsky, Valery Ortiz Jimenez, Jason Campbell, Curt Richter
This paper presents a high-endurance capacitorless one-transistor (1T) cryogenic memory, fabricated in a 180 nm bulk CMOS technology, with a high memory window of (107 I1/I0 sense current ratio) and prolonged retention. The memory is enabled by the

WLAN Protocols Identification Using Machine Learning and Ensemble Models

January 7, 2025
Author(s)
Akimun Jannat Alvina, Yao Ma, Mark Golkowski
The growing demand for wireless communications has caused significant spectrum congestion, requiring multiple WLAN protocols to share limited spectrum resources. To address this, further research is necessary to optimize spectrum sharing and improve

Kinetic inductance current sensor for visible to near-infrared wavelength transition-edge sensor readout

November 6, 2024
Author(s)
Paul Szypryt, Douglas Bennett, Ian Fogarty Florang, Joseph Fowler, Jiansong Gao, Andrea Giachero, Ruslan Hummatov, Adriana Lita, John Mates, Sae Woo Nam, Daniel Swetz, Joel Ullom, Michael Vissers, Jordan Wheeler
Single-photon detectors based on the superconducting transition-edge sensor are used in a number of visible to near-infrared applications, particularly for photon-number-resolving measurements in quantum information science. To be practical for large-scale

POTENT: Post-Synthesis Obfuscation for Secure Network-on-Chip Architectures

November 5, 2024
Author(s)
Kostas Amberiadis, Dipal Halder, Sandip Ray, Yuntao Liu, Ankur Srivastava
We develop a novel post-synthesis obfuscation technique, POTENT, to protect NoC fabrics against reverse engineering attacks. POTENT integrates programmable switches at NoC routers, concealing topology and communication paths under a dynamically controlled

Terahertz On-wafer mTRL Calibration Kits For Microelectronics Characterization

October 7, 2024
Author(s)
Jerome Cheron, Robert Jones, Bryan Bosworth, Jeffrey Jargon, Benjamin Jamroz, Ari Feldman
We report accurate small-signal measurements of heterojunction-bipolar-transistors (HBTs) that are characterized with two on-wafer multiline thru-reflect-line (mTRL) calibration kits. The first calibration kit is designed with thin-film microstrip

Summary Report: CHIPS R&D Program Standards Summit

September 27, 2024
Author(s)
Mary Bedner, Chris Greer
The mission of the National Institute of Standards and Technology's (NIST) CHIPS Research and Development Office (CHIPS R&D) under the Department of Commerce's CHIPS for America Program is to accelerate the development and commercial deployment of

IP Security in Structured ASIC: Challenges and Prospects

September 25, 2024
Author(s)
Rasheed Almawzan, Sudipta Paria, Aritra Dasgupta, Kostas Amberiadis, Swarup Bhunia
With the globalization of hardware manufacturing and the growing demand for electronics, companies now heavily rely on offshore facilities for most of the design and manufacturing processes, including emerging technologies like Structured ASICs

Quadrature amplitude modulation for electronic side and Pound-Drever-Hall locking

September 13, 2024
Author(s)
Juntian Tu, Alessandro Restelli, Tsz-Chun Tsui, Kevin Weber, Ian Spielman, James(Trey) Porto, Steven Rolston, Sarthak Subhankar
The Pound-Drever-Hall (PDH) technique is routinely used to stabilize the frequency of a free-running laser to an ultralow expansion (ULE) reference cavity. The electronic sideband (ESB) locking scheme—a variant of the standard PDH locking scheme—helps

Low Energy Spiking Neural Network using Ge4Sb6Te7 Phase-Change Memory Synapses

August 6, 2024
Author(s)
Huairuo Zhang, Albert Davydov, Shafin Hamid, Eric Pop, Asir Khan
Spiking neural networks (SNN) with Ge2Sb2Te5 (GST) based phase change memory (PCM) synaptic devices are promising for edge applications. However, from a de-vice standpoint, the performance of such SNN is often con-strained by the abrupt depression

On-Wafer Capacitor Characterization Including Uncertainty Estimates Up to 1.0 THz

July 19, 2024
Author(s)
Robert Jones, Jerome Cheron, Benjamin Jamroz, Dylan Williams, Ari Feldman, Peter Aaen, Christian Long, Nathan Orloff
In this article we extract the capacitance of shunt and series metal-insulator-metal capacitors from on-wafer S-parameter measurements in the WR1.0 waveguide band. We verify consistency of the measured devices in two different state-of-the-art terahertz

A 0.1 GHz to 1.1 THz Inverted Grounded-CPW mTRL Calibration Kit Characterization in an InP HBT Process

May 13, 2024
Author(s)
Jerome Cheron, Rob Jones, Dylan Williams, Miguel Urteaga, Bryan Bosworth, Nick Jungwirth, Jeffrey Jargon, Ben Jamroz, Chris Long, Nate Orloff, Ari Feldman, Peter Aaen
We report a novel design approach of on-wafer multiline thru-reflect-line (mTRL) calibration kit fabricated on a commercial semiconductor-based transistor process that we validate from 0.1 GHz to 1.1 THz. The on-wafer calibration standards are designed
Was this page helpful?