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POTENT: Post-Synthesis Obfuscation for Secure Network-on-Chip Architectures

Published

Author(s)

Kostas Amberiadis, Dipal Halder, Sandip Ray, Yuntao Liu, Ankur Srivastava

Abstract

We develop a novel post-synthesis obfuscation technique, POTENT, to protect NoC fabrics against reverse engineering attacks. POTENT integrates programmable switches at NoC routers, concealing topology and communication paths under a dynamically controlled key to make the design resilient to reverse-engineering attempts. By targeting post-synthesis gate-level netlist, POTENT overcomes challenges induced by logic optimization that can render pre-synthesis (RTL-level) NoC obfuscations vulnerable to SAT attacks. We extensively evaluate POTENT to demonstrate its robustness to SAT attacks. Finally, our experiments show that POTENT incurs minimal overhead on area, power, and performance.
Proceedings Title
2024 IEEE 37th International System-on-Chip Conference (SOCC)
Conference Dates
September 16-19, 2024
Conference Location
Dresden, DE
Conference Title
IEEE SOCC 2024

Keywords

Network-on-Chip (NoC), System-on-Chip (SoC), Post-synthesis obfuscation, Reverse engineering attacks

Citation

Amberiadis, K. , Halder, D. , Ray, S. , Liu, Y. and Srivastava, A. (2024), POTENT: Post-Synthesis Obfuscation for Secure Network-on-Chip Architectures, 2024 IEEE 37th International System-on-Chip Conference (SOCC), Dresden, DE, [online], https://doi.org/10.1109/SOCC62300.2024.10737820, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=957934 (Accessed December 13, 2024)

Issues

If you have any questions about this publication or are having problems accessing it, please contact reflib@nist.gov.

Created November 5, 2024, Updated November 26, 2024