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Metrology for Nanosystems and Nanoelectronics Reliability Assessments

Published

Author(s)

Yaw S. Obeng, Chukwudi A. Okoro, Joseph J. Kopanski

Abstract

The traditional models and techniques for studying reliability in integrated circuits may not be appropriate for nanoelectronics and nanosystems. In this paper, we present an overview of a number of materials and metrology techniques currently under development in our group at NIST. Among other topics, we will assess the techniques and models currently used for evaluating integrated circuit reliability, as well as present some new approaches.
Proceedings Title
TBD
Conference Dates
August 20-23, 2012
Conference Location
Birmingham
Conference Title
12th IEEE NanoTechnology Conference,

Keywords

CBCM, charge based capacitance measurement, interconnects, metrology techniques, nanoelectronics, reliability, three-dimensional integrated circuits, through silicon vias, TSVs

Citation

Obeng, Y. , Okoro, C. and Kopanski, J. (2012), Metrology for Nanosystems and Nanoelectronics Reliability Assessments, TBD, Birmingham, -1, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=911433 (Accessed May 24, 2024)

Issues

If you have any questions about this publication or are having problems accessing it, please contact reflib@nist.gov.

Created August 20, 2012, Updated February 19, 2017