Skip to main content
U.S. flag

An official website of the United States government

Official websites use .gov
A .gov website belongs to an official government organization in the United States.

Secure .gov websites use HTTPS
A lock ( ) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.

Design and Fabrication of a Copper Test Structure as a Electrical Critical Dimension Reference

Published

Author(s)

Byron J. Shulver, Andrew S. Bunting, Alan Gundlach, Les I. Haworth, Alan W. Ross, Anthony J. Snell, J. T. Stevenson, Anthony Walton, Richard A. Allen, Michael W. Cresswell

Abstract

A novel copper damascene process is reported for the implementation of Electrical Critical Dimension (ECD) reference material. The method of fabrication first creates an initial 'silicon preform' whose linewidth is transfered into a trench using a silicon nitride mould. The trench is created by removing a portion of the silicon and replacing it with copper to enable both Transmission Electron Microscopy (TEM) and electrical linewidth measurements to be made on the same structure. The techniqueis based on the use anisotropic wet etching of (110) silicon wafers to yield silicon features with vertical sidewalls. The paper demonstrates that this method successful produces copper lines which serve as ECD control structures and the process can be applied to any damascene compatible material for developing electrical linewidth measurement reference material.
Proceedings Title
Proc., IEEE International Conference on Microelectronic Test Structures
Conference Dates
March 6-9, 2006
Conference Location
Austin, TX, USA

Keywords

Chemical Mechanical Polishing (CMP), copper, Critical dimension (CD), interconnect, reference material

Citation

Shulver, B. , Bunting, A. , Gundlach, A. , Haworth, L. , Ross, A. , Snell, A. , Stevenson, J. , Walton, A. , Allen, R. and Cresswell, M. (2006), Design and Fabrication of a Copper Test Structure as a Electrical Critical Dimension Reference, Proc., IEEE International Conference on Microelectronic Test Structures, Austin, TX, USA (Accessed March 29, 2024)
Created March 31, 2006, Updated October 12, 2021