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Brian Hoskins ()

Physicist

Brian Hoskins is a research physicist in the Alternative Computing Group in the Nanoscale Device Characterization Division of the Physical Measurement Laboratory (PML). He received both a B.S. and an M.S. in Materials Science and Engineering from Carnegie Mellon University and a Ph.D. in Materials from the University of California, Santa Barbara. For his doctoral research, he developed and characterized resistive switching devices for use in neuromorphic networks. Brian is working on CMOS integration of resistive switches for the development and characterization of intermediate scale neuromorphic networks.

Projects

Selected Publications

  • Optimized stateful material implication logic for three-dimensional data manipulation, G. C. Adam, B. D. Hoskins, M. Prezioso, D.B. Strukov, Nano Research 9, 3914 (2016). [doi]
  • Training and operation of an integrated neuromorphic network based on metal-oxide memristors, M. Prezioso*, F. Merrikh-Bayat*, B.D. Hoskins *, G.C. Adam, K.K. Likharev, and D.B. Strukov, Nature 521, 7550 (2015). [doi] *Equal Contributor
  • Resistive switching and its suppression in Pt/Nb:SrTiO3 junctions, E. Mikheev, B.D Hoskins, D. B. Strukov, and S. Stemmer, Nature Communications 5, 3990 (2014). [doi]

Publications

Layer ensemble averaging for fault tolerance in memristive neural networks

Author(s)
Osama Yousuf, Brian Hoskins, Karthick Ramu, Mitchell Fream, William Borders, Advait Madhavan, Matthew Daniels, Andrew Dienstfrey, Jabez McClelland, Martin Lueker-Boden, Gina Adam
Advancements in continual learning with artificial neural networks have been fueled in large part by scaling network dimensionalities. As this scaling continues

Advancing Measurement Science for Microelectronics: CHIPS R&D Metrology Program

Author(s)
Marla L. Dowell, Hannah Brown, Gretchen Greene, Paul D. Hale, Brian Hoskins, Sarah Hughes, Bob R. Keller, R Joseph Kline, June W. Lau, Jeff Shainline
The CHIPS and Science Act of 2022 called for NIST to "carry out a microelectronics research program to enable advances and breakthroughs....that will accelerate

Patents (2018-Present)

Quasi-Systolic Processor and Quasi-Systolic Array

NIST Inventors
Brian Hoskins , Matthew Daniels , Mark D. Stiles and Advait Madhavan
A quasi-systolic array includes: a primary quasi-systolic processor; an edge row bank and edge column bank of edge quasi-systolic processors; and an interior bank of interior quasi-systolic processors. The primary quasi-systolic processor, edge quasi-systolic processor, and interior quasi-systolic
Created May 7, 2019, Updated June 27, 2025
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