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Test Chip for Electrical Linewidth of Copper-Interconnection Features and Related Parameters

Published

Author(s)

Michael W. Cresswell, N. Arora, Richard A. Allen, Christine E. Murabito, Curt A. Richter, Ashwani K. Gupta, Loren W. Linholm, D. Pachura, P. Bendix

Abstract

This paper reports a new electrical test structure for measuring the barrier-layer thickness and total physical linewidth of copper-cored interconnect features. The test structure has four critical dimension (CD) reference segments of different drawn linewidths. A new linewidth-extraction algorithm has been developed and extensively tested with and sheet-resistance measurement emulations. It has also been applied to measurements extracted from scaled-up physical structures. A second test structure for measuring conducting feature and interlayer-dielectric (ILD) thickness by use of the charge-based capacitance method (CBCM) is located on the test chip. Test-chips featuring both of these structures have been patterned in aluminum using a standard 0.18 5m CMOS process and preliminary results are reported here.
Proceedings Title
Proc., IEEE International Conference on Microelectronic Test Structures
Volume
14
Conference Dates
March 19-22, 2001
Conference Location
Kobe, 1, JA

Keywords

barrier layer, copper interconnect , critical dimension (CD), cross-bridge resistor, linewidth, test structure, VLSI

Citation

Cresswell, M. , Arora, N. , Allen, R. , Murabito, C. , Richter, C. , Gupta, A. , Linholm, L. , Pachura, D. and Bendix, P. (2001), Test Chip for Electrical Linewidth of Copper-Interconnection Features and Related Parameters, Proc., IEEE International Conference on Microelectronic Test Structures, Kobe, 1, JA (Accessed April 21, 2024)
Created February 5, 2001, Updated October 12, 2021