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Synchrotron-Based Measurement of the Impact of Thermal Cycling on the Evolution of Stresses in Cu Through-Silicon Via

Published

Author(s)

Chukwudi A. Okoro, Lyle E. Levine, Ruqing Xu, Klaus Hummler, Yaw S. Obeng

Abstract

One of the main causes of failure during the lifetime of microelectronics devices is their exposure to fluctuating temperatures. In this work, synchrotron-based X-ray micro-diffraction is used to study the evolution of stresses in copper through-silicon via (TSV) interconnects “as-received” and after 1000 thermal cycles. For both test conditions, the significant fluctuation in the measured principal and shear stresses with depth is attributed to variations in the Cu grain orientation. The mean hydrostatic stresses along the entire length of the Cu TSV that had undergone 1000 thermal cycles (123 ± 37 MPa) were found to be 8 times greater than those of the “as-received” Cu TSVs; this effect is attributed to the increase in strain-hardening. On the other hand, the low mean hydrostatic stresses, ≈ 16 ± 44 MPa, in the “as-received” Cu TSV were the result of room temperature stress relaxation. The evolution in stresses with thermal cycling is a clear indication that the impact of Cu TSV on front-end-of-line (FEOL) device performance, will change through the lifetime of the 3D stacked dies, and ought to be accounted for during front-end-of-line (FEOL) keep-out-zone design rules development.
Citation
Journal of Applied Physics
Volume
115

Citation

Okoro, C. , Levine, L. , Xu, R. , , K. and Obeng, Y. (2014), Synchrotron-Based Measurement of the Impact of Thermal Cycling on the Evolution of Stresses in Cu Through-Silicon Via, Journal of Applied Physics, [online], https://doi.org/10.1063/1.4885461 (Accessed July 31, 2021)
Created June 30, 2014, Updated November 10, 2018