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Displaying 301 - 325 of 1445

3D Nanometrology Based on SEM Stereophotogrammetry

September 18, 2017
Author(s)
Vipin N. Tondare, John S. Villarrubia, Andras Vladar
Three-dimensional (3D) reconstruction of a sample surface from scanning electron microscope (SEM) images taken at two perspectives has been known for decades. However, this method has not been widely used in the semiconductor industry for 3D measurements

Strain Measurement of 3D Structured Nanodevices by EBSD

August 20, 2017
Author(s)
William A. Osborn, Lawrence H. Friedman, Mark D. Vaudin
We present a new methodology to accurately measure strain magnitudes from 3D nanodevices using Electron Backscatter Diffraction (EBSD). Because the dimensions of features on these devices are smaller than the interaction volume for backscattered electrons

Interface Engineering for Nanoelectronics

August 16, 2017
Author(s)
Christina A. Hacker, Robert C. Bruce, Sujitra J. Pookpanratana
Innovation in the electronics industry is tied to interface engineering as devices increasingly incorporate new materials and shrink. Molecular layers offer a versatile means of tuning interfacial electronic, chemical, physical, and magnetic properties

Structural and electrical analysis of epitaxial 2D/3D vertical heterojunctions of monolayer MoS2 on GaN

August 4, 2017
Author(s)
Albert Davydov, Terrance P. O'Regan, Andrew A. Herzing, Dimitry Ruzmetov, Robert A. Burke, Kehao Zhang, A. Glen Birdwell, DeCarlos Taylor, E Byrd, Joshua A. Robinson, Tony G. Ivanov, M R. Neupane, S D. Walck
Integrating two-dimensional (2D) and three-dimensional (3D) semiconductors to realize vertical heterojunctions with novel electronic and optoelectronic properties is gaining interest from the device community. In this study, we utilize an approach that

Comprehensive Capacitance-Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SixGe1?x and InxGa1?xAs: Part II - Fits and Extraction from Experimental Data

July 21, 2017
Author(s)
Sarkar Anwar, William Vandenberghe, Gennadi Bersuker, Dmitry Veksler, Giovanni Verzellesi, Rohit Galatage, Creighton Buie, Adam Barton, Eric Vogel, Christopher Hinkle
Capacitance-voltage (C-V) measurement and analysis is highly useful for determining important information about metal-oxide-semiconductor (MOS) gate stacks. Parameters such as the equivalent oxide thickness (EOT), substrate doping density, flatband voltage
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