The Wafer Bond Task Force of the SEMI MEMS Standards Committee has begun a round robin experiment to evaluate methods for identifying and characterizing voids in bonded wafer pairs for three-dimensional integrated circuit (3D IC) applications. Due to the numerous process steps that the wafers have undergone and the presence of Through-Silicon Vias (TSVs), bonded wafers containing 3D ICs are expected to suffer a higher rate of post-bonding voids than other bonding applications. In addition, 3D ICs will likely be more sensitive to small voids than other bond applications. In this round robin experiment eight approaches to void metrology are being compared by 13 participating laboratories to highlight the relative abilities of each of these metrologies to identify potentially killer defects.
Proceedings Title: Semiconductor Wafer Bonding 11: Science, Technology, and Applications
Conference Dates: October 10-15, 2010
Conference Location: Las Vegas, NV
Pub Type: Conferences
microelectromechanical systems (MEMS), three-dimensional integrated circuit (3D IC), wafer bonding, bond void metrology