Intercomparison of Methods for Detecting and Characterizing Voids in Bonded Wafer Pairs

Published

October 1, 2010

Author(s)

Richard A. Allen, Andrew C. Rudack, David T. Read, Winthrop A. Baylies

Abstract

The Wafer Bond Task Force of the SEMI MEMS Standards Committee has begun a round robin experiment to evaluate methods for identifying and characterizing voids in bonded wafer pairs for three-dimensional integrated circuit (3D IC) applications. Due to the numerous process steps that the wafers have undergone and the presence of Through-Silicon Vias (TSVs), bonded wafers containing 3D ICs are expected to suffer a higher rate of post-bonding voids than other bonding applications. In addition, 3D ICs will likely be more sensitive to small voids than other bond applications. In this round robin experiment eight approaches to void metrology are being compared by 13 participating laboratories to highlight the relative abilities of each of these metrologies to identify potentially killer defects.

Proceedings Title

Semiconductor Wafer Bonding 11: Science, Technology, and Applications

Conference Dates

October 10-15, 2010

Conference Location

Las Vegas, NV

Pub Type

Conferences

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Keywords

microelectromechanical systems (MEMS), three-dimensional integrated circuit (3D IC), wafer bonding, bond void metrology

Citation

Allen, R. , Rudack, A. , Read, D. and Baylies, W. (2010), Intercomparison of Methods for Detecting and Characterizing Voids in Bonded Wafer Pairs, Semiconductor Wafer Bonding 11: Science, Technology, and Applications, Las Vegas, NV, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=906152 (Accessed March 13, 2025)