Electro-physical Technique for Post-fabrication Measurements of CMOS Process Layer Thicknesses

Published

October 1, 2007

Author(s)

Janet M. Cassard, Paul T. Vernier

Abstract

This paper presents a combined physical and electrical post-fabrication method for determining the thicknesses of the various layers in a commercial 1.5-um complementary-metal-oxide-semiconductor (CMOS) foundry process available through MOSIS. Forty-two thickness values are obtained from physical step height measurements performed on thickness test structures and from electrical measurements of capacitances, sheet resistances, and resistivities. Appropriate expressions, numeric values, and uncertainties for each layer thickness are presented, along with a systematic nomenclature for interconnect and dielectric thicknesses.

Citation

Journal of Research (NIST JRES) -

Volume

112

Issue

5

NIST Pub Series

Journal of Research (NIST JRES)

Pub Type

NIST Pubs

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Keywords

CMOS, MEMS, nomenclature, platform height, step height, test structures, thickness, Young''''s modulus

Citation

Cassard, J. and Vernier, P. (2007), Electro-physical Technique for Post-fabrication Measurements of CMOS Process Layer Thicknesses, Journal of Research (NIST JRES), National Institute of Standards and Technology, Gaithersburg, MD, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=32592 (Accessed April 26, 2024)