A novel copper damascene process is reported for the implementation of Electrical Critical Dimension (ECD) reference material. The method of fabrication first creates an initial 'silicon preform' whose linewidth is transfered into a trench using a silicon nitride mould. The trench is created by removing a portion of the silicon and replacing it with copper to enable both Transmission Electron Microscopy (TEM) and electrical linewidth measurements to be made on the same structure. The techniqueis based on the use anisotropic wet etching of (110) silicon wafers to yield silicon features with vertical sidewalls. The paper demonstrates that this method successful produces copper lines which serve as ECD control structures and the process can be applied to any damascene compatible material for developing electrical linewidth measurement reference material.
Proceedings Title: Proc., IEEE International Conference on Microelectronic Test Structures
Conference Dates: March 6-9, 2006
Conference Location: Austin, TX
Pub Type: Conferences
Chemical Mechanical Polishing (CMP), copper, Critical dimension (CD), interconnect, reference material