Reliability Test Chips: NIST 33 & NIST 34 for JEDEC Inter-Laboratory Experiments and More

Published

December 31, 1998

Author(s)

Harry A. Schafft

Abstract

Two reliability test patterns, NIST 33 and NIST 34, are being designed, and a third, NIST 36, is being planned to be used in a number of inter-laboratory experiments as part of the activities of the Metal Reliability Task Group of the EIA/JEDEC Committee JC 14.2 on Wafer Level Reliability. These chips will also be used for other tasks, many of which will provide additional characterization data in support of the JEDEC inter-laboratory experiments.The immediate use of NIST 33 is to perform inter-laboratory experiments to determine the within-laboratory and the between-laboratory precision of two JEDEC standard test methods: the isothermal test (JESD63) and the SWEAT test (JEP119). These experiments are intended also to determine the impact of modifications of the designs of test structures used in this electromigration accelerated stress tests. Supplemental to these experiments will be one to determine the precision of the ASTM standard electromigration stress test (F1260).

Proceedings Title

Proc., 1997 IEEE International Integrated Reliability Workshop

Conference Dates

October 13-16, 1997

Conference Location

Lake Tahoe, CA

Pub Type

Conferences

Keywords

EIA/JEDEC, electromigration, linewidth, reliability

Citation

Schafft, H. (1998), Reliability Test Chips: NIST 33 & NIST 34 for JEDEC Inter-Laboratory Experiments and More, Proc., 1997 IEEE International Integrated Reliability Workshop, Lake Tahoe, CA (Accessed December 12, 2024)