NOTICE: Due to a lapse in annual appropriations, most of this website is not being updated. Learn more.
Form submissions will still be accepted but will not receive responses at this time. Sections of this site for programs using non-appropriated funds (such as NVLAP) or those that are excepted from the shutdown (such as CHIPS and NVD) will continue to be updated.
An official website of the United States government
Here’s how you know
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
Secure .gov websites use HTTPS
A lock (
) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.
Issues with Electrical Characterization of Advanced Gate Dielectrics in Metal-oxide-semiconductor devices
Published
Author(s)
Eric M. Vogel
Abstract
Experimental measurements and simulations are used to provide an overview of key issues with the electrical characterization of metal-oxide-semiconductor (MOS) devices with ultra-thin oxide and alternate gate dielectrics. Experimental issues associated with the most common electrical characterization method, capacitance-voltage (C-V) are first described. Issues associated with equivalent oxide thickness extraction and comparison, interface state measurement, and defect generation are then overviewed.
Proceedings Title
Proc., Workshop on Dielectrics in Microelectronics
Vogel, E.
(2002),
Issues with Electrical Characterization of Advanced Gate Dielectrics in Metal-oxide-semiconductor devices, Proc., Workshop on Dielectrics in Microelectronics, Grenoble, FR
(Accessed October 27, 2025)