Extensions to the recommended practices for GD&T in STEP-AP210 in the context of packaged electronic components

Published

December 4, 2009

Author(s)

Jamie Stori, Kevin G. Brady, Thomas Thurman

Abstract

The purpose of this document is to extend the recommended practices for the representation of GD&T in STEP (ISO-10303) within the context of packaged electronic component models represented in AP210 (ISO-10303:210). The recommendations in this document are intended to be consistent with the current GD&T accepted practice in STEP. Please refer to the document entitled "Recommended Practices for Dimensions, Dimensional and Geometric Tolerances" dated December 6, 2006 by David Briggs, Tom Hendrix, and Steve Yates for current practice recommendations for GD&T in STEP. This document is available on the website of the CAx Implementor Forum (http://www.cax-if.org/) under the Recommended Practices link. The ARM application objects, relationships, attributes, and mapping to the corresponding MIM entities, relationships, and attributes have been updated to the IS version of the 2nd Edition of AP-210. The largest family of standards for packaged electronic components are those published by JEDEC. The JEDEC standards are freely and publicly available, and contain detailed dimensioned and toleranced specifications for physical package configurations. JEDEC Publication 95 is a series of documents containing specifications for many common physical package configurations. The JEDEC Publication 95 documents can be accessed on-line at: http://www.jedec.org/DOWNLOAD/pub95/default.cfm. In this document, in addition to general guidelines for the representation of tolerances in a packaged electronic component, a set of STEP mappings for a typical toleranced JEDEC package model will be discussed. These examples are intended to be representative of many of the common tolerances encountered in the JEDEC standards. The GD&T standard referenced by both JEDEC and the 2006 STEP recommended practice is ASME Y14.5 (1994). The recommendations in this document are intended to be consistent with both the 1994 as well as recent 2009 publication of Y14.5.

Citation

NIST Interagency/Internal Report (NISTIR) - 7634

Report Number

7634

NIST Pub Series

NIST Interagency/Internal Report (NISTIR)

Pub Type

NIST Pubs

Download Paper

Local Download

Keywords

STEP, AP210, Modeling, PCA, Circuit Board

Citation

Stori, J. , Brady, K. and Thurman, T. (2009), Extensions to the recommended practices for GD&T in STEP-AP210 in the context of packaged electronic components, NIST Interagency/Internal Report (NISTIR), National Institute of Standards and Technology, Gaithersburg, MD, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=903904 (Accessed April 19, 2024)