Experimental investigation of the dielectric-semiconductor interface with scanning capacitance microscopy

Published

December 20, 2004

Author(s)

Jihui Yang, Joseph Kopanski, A Postula, M Bialkowski

Abstract

An experimental investigation of how interface states effect scanning capacitance microscopy (SCM) measurements is presented. Different sample polishing procedures were used to make SCM samples that would have different interface state densities, but identical oxide thicknesses. By comparing SCM signals of these samples, the effect of interface states could be singled out. The interface states of these SCM samples were found to have an amphoteric energy distribution. The magnitude of the maximum SCM signals (maximum dC/dV in dC/dV versus dc bias, Vdc, plots) is independent of the interface-trapped charges, while the full width at half maximum (FWHM) of the dC/dV-Vdc curves is broadened with the interface states. The physics of SCM interface states effect is also discussed.

Citation

Microelectronics Reliability

Volume

45

Pub Type

Journals

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Keywords

dielectric, interface trapped charge, scanning capacitance microscopy, SiO2, surface states

Citation

Yang, J. , Kopanski, J. , Postula, A. and Bialkowski, M. (2004), Experimental investigation of the dielectric-semiconductor interface with scanning capacitance microscopy, Microelectronics Reliability, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=31737 (Accessed October 20, 2025)