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DESIGN OF TEST STRUCTURE FOR 3D-STACKED INTEGRATED CIRCUITS (3D-SICS) METROLOGY

Published

Author(s)

Lin You, Jungjoon Ahn, Joseph Kopanski
Proceedings Title
2013 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics
Conference Dates
March 25-28, 2013
Conference Location
Gaithersburg, MD, US

Citation

You, L. , Ahn, J. and Kopanski, J. (2014), DESIGN OF TEST STRUCTURE FOR 3D-STACKED INTEGRATED CIRCUITS (3D-SICS) METROLOGY, 2013 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics, Gaithersburg, MD, US (Accessed May 24, 2024)

Issues

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Created March 24, 2014, Updated October 12, 2021