Skip to main content
U.S. flag

An official website of the United States government

Official websites use .gov
A .gov website belongs to an official government organization in the United States.

Secure .gov websites use HTTPS
A lock ( ) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.

Back-End-of-Line Test Structure Design and Simulation for Subsurface Metrology with Scanning Probe Microscopy



Lin You, Emily Hitz, Jungjoon Ahn, Yaw S. Obeng, Joseph J. Kopanski


As demands in the semiconductor industry call for further miniaturization and performance enhancement of electronic systems, the traditional planar (2D) electronic interconnection and packaging technologies show their difficulties in meeting the ever-advancing standards of the industry. To overcome such limitations, 3D stacked integrated circuits (3D-SICs) draw tremendous research interest and have been widely studied.[1] In the end, the billions of transistors are interconnected with tens of kilometers of wires that packed into an area of square centimeters, making a giant “metallic forest”.[2-4] The complexity of the multi metallization levels of back-end of line (BEOL) brings challenges such as resistive-capacitive (RC) delay and reliability issues. From the metrology point of view, traditional scanning probe microscopy (SPM) technologies show mature capabilities of acquiring the surface metrology. However, additional capabilities such as subsurface imaging and electromagnetic property extraction in nano-scale are required to solve BEOL problems. Recently, several techniques, such as scanning microwave microscopy (SMM), electrostatic force microscopy (EFM) and Kelvin probe force microscopy (KFM) have shown their promising capability of subsurface characterization on different semiconductor devices. [5, 6] To enhance our SPM subsurface metrology capabilities and determine more accurately the limitations of the technique, we will compare experimental and simulation results. A multi-level test chip with several well-known buried structures has been designed and will be integrated on a thumb-nail size chip. Pads will be bonded on a printed circuit board (PCB), allowing external bias accesses. Different feature components can be biased separately to simulate a device under test (DUT). In this work, the surface potential distributions of opposite biased parallel buried metal lines are simulated to estimate the KFM subsurface resolution under different line depth
Conference Dates
December 11-13, 2013
Conference Location
Bethesda, MD
Conference Title
2013 International Semiconductor Device Research Symposium


BEOL, KFM, SMM, Subsurface metrology


You, L. , Hitz, E. , Ahn, J. , Obeng, Y. and Kopanski, J. (2013), Back-End-of-Line Test Structure Design and Simulation for Subsurface Metrology with Scanning Probe Microscopy, 2013 International Semiconductor Device Research Symposium, Bethesda, MD (Accessed June 20, 2024)


If you have any questions about this publication or are having problems accessing it, please contact

Created December 13, 2013, Updated February 19, 2017