Analysis of Leakage Currents and Impact on Off-State Power Consumption for CMOS Technology in the 100 nm Regime
W. K. Henson, N. Yong, S. Kubicek, Eric M. Vogel, J. J. Wortman, K. De Meyer, A. Naem
The off-state leakage currents have been investigated for sub 100 nm CMOS technology. The two leakage mechanisms investiaged in this work include the conventional off-state leakage due to short channel effects and the gate leakage through ultra-thin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: 1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and 2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 nm to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 nm to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggest that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications.
IEEE Transactions on Electron Devices
MOS devices, ultrathin gate oxide, off-state leakage, power consumption
, Yong, N.
, Kubicek, S.
, Vogel, E.
, Wortman, J.
, De Meyer, K.
and Naem, A.
Analysis of Leakage Currents and Impact on Off-State Power Consumption for CMOS Technology in the 100 nm Regime, IEEE Transactions on Electron Devices
(Accessed December 11, 2023)