Time-resolved-emission microscopy (TREM) is a workhorse of semiconductor circuit evaluation. However, as transistor dimensions and power-supply voltages have been reduced, transistor emission has become fainter and signals from multiple transistors are convoluted. The 2023 roadmap from the Electronic Device Failure Analysis Society documents the need for improvements in TREM for circuit analysis of advanced technology nodes. Improving the sensitivity and number of pixels in the sensor arrays are primary objectives for meeting these needs.
This project will improve TREM by tailoring NIST’s single-photon detectors to this purpose and scaling up these sensors to the megapixel level.
Grand Challenge 4. Modeling and Simulating Semiconductor Materials, Designs, and Components
When a new integrated circuit is fabricated, it is necessary to measure the chip with microscopy techniques such as photon emission microscopy, which look at infrared photons emitted by electrons accelerated in transistor channels. TREM, also referred to as picosecond imaging circuit analysis, is a variant of this technique that makes use of the temporal information of the emitted photons to precisely determine transistor switching activity in time. With this technique, faint photonic signals generated by transistors are imaged, and the timing information of the photons reveals transistor switching activity. The data from these measurements show which circuit blocks are performing as expected, provide locations of faults, highlight timing errors due to parasitics, and map power consumption. Two problems have arisen in the past decade: 1) transistors have become much smaller, with 100 transistors located in a diffraction-limited spot, and 2) the power-supply voltage (Vdd) has been reduced to around 0.7 V, which results in much fainter emission shifted into the mid-infrared. Current TREM signal are extremely faint, requiring long integration. Identifying errant transistors has become much more difficult, with signals from 100 transistors impinging on a single sensor.
To overcome these problems, three advances are required:
The TREM technique was developed to inform circuit models at all levels of physics from electron transport to SPICE level, providing granular information on signal integrity, reliability, and power consumption. TREM measurements provide this information across all operating temperatures, drive frequencies, and bias conditions. Further a major component of this project will be to develop new AI algorithms to gain further insights from the measured data.
Our approach will enable the disambiguation of authentic chips from counterfeits, identification of the technology node used to manufacture the chip, post-foundry tamper-detection, and possibly the discovery of the entire netlist of an unknown integrated circuit within one day. These insights are highly relevant to hardware security, particularly for critical-path components used in the context of national security, as has been communicated to us by IARPA and the Air Force.
Within the first year, we will advance beyond present capabilities by incorporating our superconducting-nanowire single-photon detectors (SPDs) in existing TREM systems. Our team has demonstrated SPDs with >98% system-detection efficiency and operation in the mid-IR. These advantages will yield an immediate improvement of at least 50x in measurement throughput. We will also quantify the spectrum of photon emission, which is essential to predict the signal-to-noise ratio of future systems.
By the end of the program we aspire to advance from using one pixel up to ten-thousand pixels by advancing the readout circuitry of our sensors, which can be accomplished through the monolithic integration of semiconductor components with our superconducting detectors. Our team is equipped to achieve this advance due to competency with photonic sensors, superconducting electronics, and semiconductor devices. Calculations indicate potential to deliver a 105 increase in measurement throughput for TREM.