Joseph J. Kopanski (Assoc)

Mr. Kopanski is an Electrical Engineer in the Nanoscale Device Characterization Division of the Physical Measurement Laboratory (PML) at the National Institute of Standards and Technology (NIST). His graduate research concerned development of processes and metrology for silicon carbide MOSFETs and diodes under the sponsorship of NASA Lewis Research Center (now the Glenn Research Center). He joined the then National Bureau of Standards (now NIST), Semiconductor Electronics Division as an Electrical Engineer in 1985.

At NIST, his recent research has been directed towards developing quantitative metrology techniques based on scanning probe microscopes for semiconductor and dielectric characterization, including scanning capacitance microscopy and scanning Kelvin probe microscopy. He built one of the world’s first scanning capacitance microscopes and developed much of the theory and procedures used to extract quantitative dopant profiles from SCM capacitance images of two-dimensional pn-junctions. He helped organize or chaired the 2003/2005/2007 International Workshops on INSIGHT into Semiconductor Device Fabrication, Metrology and Modeling. More recent work has focused on using the scanning microwave microscope for sub-surface imaging to determine the electrical properties of buried structures and interfaces.

He was awarded the U.S. Department of Commerce Bronze Medal Award for Superior Federal Service twice, in 2000 and 2002. In 2005, he served a term in the NIST Director's Program Office as a Program Analyst. He is author of over 80 publications and has given recent invited talks at CPEM 2014 and the Electrochemical Society, Symposium on Dielectrics for Nanosystems 2015. He is chair of the IEEE Electron Device Society Washington/Northern Virginia local Section. He is a member of ECS, MRS, APS, and a senior member of the IEEE. He is also a Co-Director of the NIST Summer Undergraduate Research Fellowship (SURF) Program for PML.

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