Electrical Test Structure for Overlay Metrology Referenced to Absolute Length Standards

Published

May 1, 1994

Author(s)

Michael W. Cresswell, William B. Penzes, Robert Allen, L Linholm, C Ellenwood, E C. Teague

Abstract

This test structure is based on the voltage-dividing potentiometer principle and was originally replicated in a single lithography cycle to evaluate feature placement by a primary pattern generator. A new test structure has now been developed from the single-cycle version and has been used for measuring the overlay of features defined by two different exposures with a stepping projection aligner. The as-measured overlay values are processed by an algorithm that minimizes the effects of nominal random pattern imperfections. The algorithm further partitions measurements of overlay into contributions that derive, respectively, from misregistration of the image fields projected by the two masks and from the drawn misplacement of features on the masks. The numerical estimates of these contributions so obtained from the electrical measurements were compared with those extracted from the same features by the NIST line scale interferometer, providing traceability to absolute length standards. The two sets of measurements were found to agree to within the several-nanometer uncertainty cited for the line scale interferometer's readings alone.

Proceedings Title

Proceedings of SPIE

Volume

2196

Conference Dates

March 2, 1994

Conference Location

San Jose, CA, USA

Conference Title

Integrated Circuit Metrology, Inspection, and Process Control VIII Marylyn H. Bennett, Editor

Pub Type

Conferences

Citation

Cresswell, M. , Penzes, W. , Allen, R. , Linholm, L. , Ellenwood, C. and Teague, E. (1994), Electrical Test Structure for Overlay Metrology Referenced to Absolute Length Standards, Proceedings of SPIE, San Jose, CA, USA (Accessed April 26, 2024)