Cheung, K.
and Suehle, J.
(2008),
The Challenge of Measuring Defects in Nanoscale Dielectrics, 213th ECS meeting: Dielectrics for Nanosystems, Phoenix, AZ
(Accessed October 14, 2025)
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
Secure .gov websites use HTTPS
A lock (
) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.
The Challenge of Measuring Defects in Nanoscale Dielectrics
Published
Author(s)
,
Abstract
Defects in nanoscale gate dielectric of MOS devices can exchange charges with the substrate via quantum mechanical tunneling. This characteristic has been utilized in many measurement methods to measure the defects and its spatial distribution. In some cases, the quantitative relationship between tunneling time and defect depth can be established. In other cases, this is not yet possible due to the lack of knowledge about the interface trap-fill time. As gate dielectrics reaches less than 1 nm equivalent oxide thickness, the measurement techniques must be made at higher speeds. Measurement into the GHz range will be needed.Proceedings Title
213th ECS meeting: Dielectrics for Nanosystems
Conference Dates
May 19-22, 2008
Conference Location
Phoenix, AZ
Conference Title
213th Meeting of the Electrochemical Society
Pub Type
Conferences
Keywords
CMOS, defect, gate dielectric, nano, trap-fill time, charge-pumping, noise
Citation
Issues
If you have any questions about this publication or are having problems accessing it, please contact [email protected].
Created May 26, 2008, Updated February 19, 2017