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Numerical Reproducibility at Exascale (NRE2015)


There are two plenary speakers (30 min each) and 4 technical talks (15 min presentation + 10 min Q&A). Here is the agenda:

8:30 am
 Opening + Admin Issues (agenda + SC16 SCC announcement)
8:35 am
D. Bailey
Berkeley Lab (re) & UC Davis
Numerical Reproducibility in High Performance Computing (slides)
9:05 am
M. Heroux
Addressing Reproducibility Challenges through Software Design, Benchmarking, and Editorial Policies (slides)
9:35 am
R. Iakymchuk et al.
Sorbonne, INRIA Rennes, & Perpignan U.

ExBLAS: Reproducible and Accurate BLAS Library (slides)

10:00 am

Coffee Break
10:30 am
D. Hill et al.
Blaise Pascal U.
Numerical Reproducibility for Parallel Stochastic Simulation 'Exascale Ready' (slides)
10:55 am
R. Robey
Los Alamos
Computational Reproducibility in Production Physics Applications (slides)
11:20 am
H. Nguyen
UC Berkeley
Cost of Reproducibility (slides)
11:45 am

Panel Discussion

Where:Part of SC15, Austin, TX
When:Friday morning, Nov 20, 2015
Deadline:August 16, 2015
Notifications:September 14, 2015
Full Papers:October 08, 2015
Organized by:
Walid Keyrouz (NIST) and Michael Mascagni (FSU & NIST)
Call for Participation

Experimental reproducibility is a cornerstone of the scientific method. As computing has grown into a powerful tool for scientific inquiry, computational reproducibility has been one of the core assumptions underlying scientific computing. With "traditional" single-core CPUs, documenting a numerical result was relatively straightforward. However, hardware developments over the past several decades have made it almost impossible to ensure computational reproducibility or to even fully document a computation without incurring a severe loss of performance. This loss of reproducibility started with CPUs that used out-of-order execution to improve performance. It has accelerated with recent architectural trends towards platforms with increasingly large numbers of processing elements, namely multicore CPUs and compute accelerators (GPUs, Intel Xeon Phi, FPGAs).

Programmers targeting these platforms rely on tools and libraries to produce codes or execute them efficiently. As a result, codes can run efficiently, but have execution details that can be impossible to predict and are often very difficult to understand after execution. Furthermore, parallel implementations often result in code with varying execution orders between runs, leading to nonreproducible computations. The underlying reasons are that (1) the hardware and system software allocate parallel work in ways that are not always specifiable at compile time and (2) the execution often proceeds in an opportunistic manner with the execution order changing between runs. As such, floating-point computations, which are non-commutative, can have different execution orders and execute on different processing elements between runs, leading to runs with varying results as a matter of fact. The predictability of systems is further complicated by two issues that are becoming more critical as systems grow in scale: (1) interconnect systems with latencies that are often outside the control of programmers and (2) reliability as the mean time between failure (MTBF) is now measured in hours on large systems. This situation seriously affects the ability to rely on scientific computations as a metrological substitute for experimentation!

Workshop Scope

The workshop is meant to address the scope of the problems of numerical reproducibility in HPC in general and those anticipated as we scale to Exascale machines in the next decade. We seek contributions of short papers (3--4 pages) in the areas of computational reproducibility in HPC from academic, government, and industry stakeholders. Areas of interest include, but are not limited to:

  • Case studies of reproducibility or the lack of it
  • Reproducibility issues in current HPC
  • System-level solutions
  • Algorithmic solutions
  • Software solutions
  • Uncertainty quantification in computational reproducibility
  • Fundamental numerical analysis of reproducibility
  • Future prospects
Workshop Format

The workshop will have:

  • two plenary talks with authors TBD,
  • a morning of contributed talks, and
  • a panel discussion to summarize the problem, current research, and prospects on long-term solutions.

The talks for this workshop will be refereed and a selection of submissions will be invited to submit full papers for peer-reviewed publication through ACM/IEEE SIGHPC.


Submissions of up to four pages should be formatted according to the IEEE conference format ( and submitted as a PDF document using Easychair at

Travel Support

Some limited travel support may be available.

Important Dates
  • August 16, 2015: paper submission deadline
  • September 14, 2015: acceptance notifications to authors and invitations to submit full papers
  • October 08, 2015: submission deadline for camera-ready full papers
  • Walid Keyrouz, National Institute of Standards and Technology (NIST), USA
  • Michael Mascagni, National Institute of Standards and Technology (NIST) and Florida State University, USA
Steering Committee
  • Dong H. Ahn, Lawrence Livermore National Lab, USA
  • David Bailey, UC Davis, USA
  • Michela Becchi, University of Missouri, USA
  • David R. C. Hill, Université Blaise Pascal, Clermont-Ferrand, France
  • Walid Keyrouz (co-organizer), NIST, USA
  • Xiaoye Sherry Li, Lawrence Berkeley National Laboratory, USA
  • Michael Mascagni (co-organizer), FSU/NIST, USA
  • Nathalie Revol, INRIA/ENS-Lyon, France
  • Siegfried Rump, University of Hamburg, Germany
Contact E-mail: (replace ".at." by "@")


Co-Located with Supercomputing in Austin, TX (

Created April 17, 2015, Updated September 21, 2016