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Towards the Integration of Carbon Nanotubes as Vias in Monolithic 3D Integrated Circuits

Published

Author(s)

Ann C. Chiaramonti Debay, Sten Vollebregt, Johan van der Cingel , Kees Beenakker, R. Ishihara

Abstract

Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects (vias) in 3D integrated circuits due to their excellent thermal and electrical properties. To investigate CNT electrical resistivity, test vias were fabricated using both a top-down and bottom-up process. The measured resistivity of 10 mΩ-cm is among the better values in literature. The ability to grow CNT directly on single-grain thin-film transistors (SG-TFT) was demonstrated. The electrical performance of the SG-TFT was found not to be influenced by the CNT growth.
Citation
Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers

Keywords

carbon nanotube, electrical transport, interconnects

Citation

Chiaramonti, A. , Vollebregt, S. , van, J. , Beenakker, K. and Ishihara, R. (2013), Towards the Integration of Carbon Nanotubes as Vias in Monolithic 3D Integrated Circuits, Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers (Accessed March 2, 2024)
Created March 21, 2013, Updated February 19, 2017