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SiO2/Si3N4/A12O3 Stacks on Silicon for Scaled-Down Memory Devices: Effects of Interfaces and Thermal Annealing

Published

Author(s)

M Lisiansky, A Heiman, M Kovler, Y Roizin, Igor Levin, A Gladkikh, M Oksman, R Edrei, A A. Hofman, Y Shnieder, T Claasen

Abstract

Effects of interfaces and thermal annealing on the electrical performance of the SiO2/Si3N4/A12O3 (ONA) stacks in non-volatile memory devices were investigated. Structural and electrical characterization demonstrated the principal role of the Si3N4/A12O3 and Al2O3/Metal-Gate interfaces in controlling the charge retention properties of the ONA-based memory cells. Memory cells that employ both electron and hole trapping were fabricated using a controlled oxidation of the Si3N4 surface prior to the growth of Al2O3, a high-temperature annealing of the entire stack in the N2+O2 atmosphere, and a metal gate electrode having a high work function (e.g. Pt). These devices exhibited electrical performance superior to that of their existing SiO2/Si3N4/SiO2 (SONOS) analogs featuring significantly larger memory windows, lower program/erase voltages, and enhanced charge retention characteristics.
Citation
Applied Physics Letters

Keywords

annealing, flash memory, interfaces, silicon nitride, silicon oxide

Citation

Lisiansky, M. , Heiman, A. , Kovler, M. , Roizin, Y. , Levin, I. , Gladkikh, A. , Oksman, M. , Edrei, R. , Hofman, A. , Shnieder, Y. and Claasen, T. (2021), SiO<sub>2</sub>/Si<sub>3</sub>N<sub>4</sub>/A1<sub>2</sub>O<sub>3</sub> Stacks on Silicon for Scaled-Down Memory Devices: Effects of Interfaces and Thermal Annealing, Applied Physics Letters (Accessed July 17, 2024)

Issues

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Created October 12, 2021