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Reliability of Ultra-Thin Silicon Dioxide Under Combined Substrate Hot Electron and Constant Voltage Tunneling Stress

Published

Author(s)

Eric M. Vogel, John S. Suehle, Bin Wang, Y Chen, J B. Bernstein

Abstract

An experimental investigation of breakdown and defect generation under combined substrate hot electron and tunneling electrical stress of silicon oxide ranging in thickness from 2.0 nm to 3.5 nm is reported. Using independent control of the gate current for a given substrate and gate bias, the time-to-breakdown of ultra-thin silicon dioxide under substrate hot electron stress is observed to be inversely proportional to the gate current density. The thickness dependence (2.0 nm to 3.5 nm) of substrate hot electron reliability is reported and shown to be similar to constant voltage tunneling stress. The build-up of defects measured using stress-induced-leakage-current and charge-pumping for both tunneling and substrate hot electron stress is reported. Based on these and previous results, a simple model is proposed to explain the time-to-breakdown behavior of ultra-thin oxide under simultaneous tunneling and substrate hot electron stress.
Citation
IEEE Transactions on Electron Devices
Volume
47
Issue
6

Keywords

CMOS, defects, electron, oxide, reliability, silicon, stress

Citation

Vogel, E. , Suehle, J. , Wang, B. , Chen, Y. and Bernstein, J. (2000), Reliability of Ultra-Thin Silicon Dioxide Under Combined Substrate Hot Electron and Constant Voltage Tunneling Stress, IEEE Transactions on Electron Devices (Accessed April 20, 2024)
Created May 31, 2000, Updated October 12, 2021