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Reliability of SiC MOS Devices

Published

Author(s)

Ranbir Singh, Allen R. Hefner Jr.

Abstract

Fundamental limitations to oxide reliability are analyzed in silicon carbide based devices. A barrier height primarily determined by band offsets between metal/SiC and the dielectric, and the electric field in the dielectric results in tunneling current into the dielectric, resulting in its degradation. Since band offsets for SiC to most dielectrics are smaller than those with respect to Si, a lower reliability is expected for SiC-dielectric based devices as compared to Si MOS devices. Other researchers have correlated interface states in the SiC-Oxide as tunneling sites that increase gate leakage currents, and influence the barrier to tunneling. Depending on the allowed maximum electric field in the gate oxide, there exists a trade-off between on-state resistance and SiC MOS reliability.
Citation
Journal of Solid-state Electronics
Volume
48
Issue
10-11

Citation

Singh, R. and Hefner Jr., A. (2004), Reliability of SiC MOS Devices, Journal of Solid-state Electronics, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=31577 (Accessed April 12, 2024)
Created June 23, 2004, Updated October 12, 2021