Suehle, J.
(2004),
Reliability Implications of Scaling Gate Oxides in Deep Submicron CMOS Technologies, GOMAC Digest of Technical Papers, Monterey, CA
(Accessed July 1, 2025)
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
Secure .gov websites use HTTPS
A lock (
) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.
Reliability Implications of Scaling Gate Oxides in Deep Submicron CMOS Technologies
Published
Author(s)
Abstract
Decreasing the thickness of the gate insulator in advanced CMOS devices seriously shrinks their reliability margin. Fortunately, dielectric breakdown becomes softer for thinner dielectrics and it has been shown in recent studies that the breakdown event has become so soft that in some cases circuit functionality is not significantly affected. This paper discusses the implications of scaling the thickness of gate dielectrics on long-term device reliability in ionizing radiation environments.Proceedings Title
GOMAC Digest of Technical Papers
Conference Dates
March 15-18, 2004
Conference Location
Monterey, CA
Conference Title
GOMACTech
Pub Type
Conferences
Citation
Issues
If you have any questions about this publication or are having problems accessing it, please contact [email protected].
Created March 18, 2004, Updated January 27, 2020