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Reliability Implications of Scaling Gate Oxides in Deep Submicron CMOS Technologies

Published

Author(s)

John S. Suehle

Abstract

Decreasing the thickness of the gate insulator in advanced CMOS devices seriously shrinks their reliability margin. Fortunately, dielectric breakdown becomes softer for thinner dielectrics and it has been shown in recent studies that the breakdown event has become so soft that in some cases circuit functionality is not significantly affected. This paper discusses the implications of scaling the thickness of gate dielectrics on long-term device reliability in ionizing radiation environments.
Proceedings Title
GOMAC Digest of Technical Papers
Conference Dates
March 15-18, 2004
Conference Location
Monterey, CA
Conference Title
GOMACTech

Citation

Suehle, J. (2004), Reliability Implications of Scaling Gate Oxides in Deep Submicron CMOS Technologies, GOMAC Digest of Technical Papers, Monterey, CA (Accessed May 19, 2024)

Issues

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Created March 18, 2004, Updated January 27, 2020