Doped semiconductor structures with ultra-sharp dopant confinement, minimal lattice defects, and high carrier concentrations are essential attributes in the development of both ultra- scaled conventional semiconductor devices and emerging all-silicon quantum computers. In addition, as semiconductor devices scale down to the sub-5 nm regime, determining the exact dopant locations with sub-nm accuracy/precision after a complete fabrication process becomes increasingly critical to understanding device performance and achieving successful device fabrication. Advanced Hydrogen Lithography techniques using scanning probes have enabled deterministic placement of single phosphorus dopants into the Si (100) surface lattice with atomic precision. However, dopant segregation, diffusion, and poor epitaxy during the device encapsulation process introduces potentially large uncertainties to the exact locations of dopant atoms. Minimizing these effects is a key to realizing the potential of atomically precise fabrication. In this study, we systematically investigate the use of locking layers (LL) to suppress dopant movement during low-temperature encapsulation overgrowth and to optimize the dopant confinement, epitaxial quality, and transport properties of the phosphorus- doped 2D layer. We use secondary ion mass spectroscopy (SIMS), scanning tunneling microscopy (STM), transmission electron spectroscopy (TEM), Atom Probe (AP) and low-temperature transport measurements to fine-tune the LL thickness, growth rate, and thermal anneal and elucidate their respective roles in optimizing the delta layer quality. We statistically quantify the dopant movement in the overgrowth direction by extracting the actual dopant concentration depth profiles using numerical simulations.
Pub Type: Journals
silicon, phosphorus, monolayer, delta-layer, segregation, locking layer