Obrzut, J.
, Ferguson, J.
and Azarian, M.
(2012),
Power Density Rating for Embedded Resistors, IPC D-54 Embedded Devices Test Methods Subcommittee, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=905275, http://www.ipc.org/CommitteeDetail.aspx?Committee=D-54
(Accessed April 26, 2024)
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
Secure .gov websites use HTTPS
A lock (
) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.
Power Density Rating for Embedded Resistors
Published
Author(s)
, Jason D. Ferguson, MIchael H. Azarian
Abstract
The Power Density Ratting (PDR) for Embedded Resistors test method covers procedures for the demonstration of the ability to operate the embedded device safely within nominal tolerance, at rated power, and to withstand the transient voltage waves resulting from switching or momentary voltage surges in the power bus without a permanent change in the electrical characteristic of the device. The procedure consists of monitoring a resistance change from its nominal value as a function of the dissipated power. During the test, the applied voltage is increased from a typical operational level until the change in the measured resistance exceeds the tolerance criteria for the device. The results are presented in terms of the dissipated power density rating (PDR) factor for the embedded resistive device. The test can be also useful in process control, quality acceptance, reliability projections, and in determining the suitability of the device material for specific applications and environmental conditions.Citation
IPC D-54 Embedded Devices Test Methods Subcommittee
Volume
IPC-TM-650
Pub Type
Websites
Download Paper
Keywords
embedded resistors, power dissipation, test method
Citation
Created July 9, 2012, Updated February 19, 2017