New Way of Handling Dimensional Measurement Results for Integrated Circuit Technology

Published

May 1, 2003

Author(s)

Michael T. Postek, John S. Villarrubia, Andras Vladar

Abstract

The international guidelines for correct expression of measurement results and errors call for a through assessment of the errors, their origin and behavior. The various dimensional measurement methods have different types of errors, different signal-to-noise ratios, sampling, signal processing schemes, etc. These methods are better or worse in several different ways but without a common way of handling them one cannot make valid comparisons. If the results of various metrology methods are handled appropriately, valid comparisons of the quality and performance characteristics of dimensional metrology methods and individual tools become possible. Currently, because no dimensional metrology tool comes with the measurement parameters and errors fully explored and thus properly known, the data collected may be often not the right kind or not enough, causing more or less invalid measurements and loss of control over the IC process. Otherwise the use of more than necessary measurement time and the collection of too much data result in a loss of throughput. Through an assessment of a current laboratory SEM with methods fully applicable to CD-SEMs, this presentation describes a way of handling and expressing measurement results and the errors associated with them, and it provides new ways for instrument optimization and accurate dimensional metrology for integrated circuit technology.

Proceedings Title

Proceedings of SPIE

Volume

5038

Conference Dates

February 24, 2003

Conference Location

Santa Clara, CA

Conference Title

Metrology, Inspection, and Process Control for Microlithography XVII
Daniel J. Herr, Editor

Pub Type

Conferences

Keywords

comparison, error, measurement, scanning electron microscope, SEM

Citation

Postek, M. , Villarrubia, J. and Vladar, A. (2003), New Way of Handling Dimensional Measurement Results for Integrated Circuit Technology, Proceedings of SPIE, Santa Clara, CA (Accessed April 20, 2024)