Skip to main content

NOTICE: Due to a lapse in annual appropriations, most of this website is not being updated. Learn more.

Form submissions will still be accepted but will not receive responses at this time. Sections of this site for programs using non-appropriated funds (such as NVLAP) or those that are excepted from the shutdown (such as CHIPS and NVD) will continue to be updated.

U.S. flag

An official website of the United States government

Official websites use .gov
A .gov website belongs to an official government organization in the United States.

Secure .gov websites use HTTPS
A lock ( ) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.

Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing

Published

Author(s)

Pragya Shrestha, Jason Campbell, Wriddhi Chakraborty, A Gupta, R Saligram, S Spetalnick, A Raychowdhury, Suman Datta

Abstract

Cryogenic computing requires high-density on-die cache memory with low latency, high bandwidth and energy-efficient access to increase cache hit and maximize processor performance. Here, we experimentally demonstrate, high-speed multi-bit memory operation in 1T SiGe Floating-body RAM (FBRAM) using 22nm FDSOI transistor at 77K, for cryogenic cache memory application. The 1T SiGe FBRAM cell (W/LG=170nm/20nm) at 77K exhibits : (a) record write time of <5ns with write voltage (VWrite) 1.5V; (b) high sense current (IRead,175μA) with read a (IRead=IRead,1-IRead,0) 14 μA; (c) 2-bit/cell operation; (d) pseudo-static retention (8x103 s) for single-bit and worst case retention of 100 s for 2-bit per cell, and (e) high write endurance >1012. Array-level benchmarking shows that compared to 6T SRAM, 1T SiGe FBRAM shows 8.3x higher memory density with 2.3x/1.8x gain in read/write energy, 3.3x/1.7x in read/write latency and 4.6x in energy-delay product (EDP) for a cache size of 16MB at 77K. Considering the cooling energy cost, FBRAM exhibit 60% EDP reduction compared to 300K 6T SRAM. Hence, SiGe FBRAM is a promising option for L2/L3 cache in high-performance cryo-computing.
Conference Dates
June 12-17, 2022
Conference Location
Honolulu, HI, US
Conference Title
2022 IEEE Symposium on VLSI Technology and Circuits

Citation

Shrestha, P. , Campbell, J. , Chakraborty, W. , Gupta, A. , Saligram, R. , Spetalnick, S. , Raychowdhury, A. and Datta, S. (2022), Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing, 2022 IEEE Symposium on VLSI Technology and Circuits, Honolulu, HI, US, [online], https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830483, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=934713 (Accessed October 9, 2025)

Issues

If you have any questions about this publication or are having problems accessing it, please contact [email protected].

Created July 22, 2022, Updated November 29, 2022
Was this page helpful?