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Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing



Pragya Shrestha, Jason Campbell, Wriddhi Chakraborty, A Gupta, R Saligram, S Spetalnick, A Raychowdhury, Suman Datta


Cryogenic computing requires high-density on-die cache memory with low latency, high bandwidth and energy-efficient access to increase cache hit and maximize processor performance. Here, we experimentally demonstrate, high-speed multi-bit memory operation in 1T SiGe Floating-body RAM (FBRAM) using 22nm FDSOI transistor at 77K, for cryogenic cache memory application. The 1T SiGe FBRAM cell (W/LG=170nm/20nm) at 77K exhibits : (a) record write time of <5ns with write voltage (VWrite) 1.5V; (b) high sense current (IRead,175μA) with read a (IRead=IRead,1-IRead,0) 14 μA; (c) 2-bit/cell operation; (d) pseudo-static retention (8x103 s) for single-bit and worst case retention of 100 s for 2-bit per cell, and (e) high write endurance >1012. Array-level benchmarking shows that compared to 6T SRAM, 1T SiGe FBRAM shows 8.3x higher memory density with 2.3x/1.8x gain in read/write energy, 3.3x/1.7x in read/write latency and 4.6x in energy-delay product (EDP) for a cache size of 16MB at 77K. Considering the cooling energy cost, FBRAM exhibit 60% EDP reduction compared to 300K 6T SRAM. Hence, SiGe FBRAM is a promising option for L2/L3 cache in high-performance cryo-computing.
Conference Dates
June 12-17, 2022
Conference Location
Honolulu, HI, US
Conference Title
2022 IEEE Symposium on VLSI Technology and Circuits


Shrestha, P. , Campbell, J. , Chakraborty, W. , Gupta, A. , Saligram, R. , Spetalnick, S. , Raychowdhury, A. and Datta, S. (2022), Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing, 2022 IEEE Symposium on VLSI Technology and Circuits, Honolulu, HI, US, [online],, (Accessed April 17, 2024)
Created July 22, 2022, Updated November 29, 2022