NOTICE: Due to a lapse in annual appropriations, most of this website is not being updated. Learn more.
Form submissions will still be accepted but will not receive responses at this time. Sections of this site for programs using non-appropriated funds (such as NVLAP) or those that are excepted from the shutdown (such as CHIPS and NVD) will continue to be updated.
An official website of the United States government
Here’s how you know
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
Secure .gov websites use HTTPS
A lock (
) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.
Modeling early breakdown failures of gate oxide in SiC power MOSFETs
Published
Author(s)
Zakariae Chbili, Asahiko Matsuda, Jaafar Chbili, Jason T. Ryan, Jason P. Campbell, Mhamed Lahbabi, D. E. Ioannou, Kin P. Cheung
Abstract
One of the most serious technology roadblocks for SiC DMOSFETs is the significant occurrence of early failures in time-dependent-dielectric-breakdown (TDDB) testing. Conventional screening methods have proved ineffective because the remaining population is still plagued with poor reliability. The traditional local thinning model for extrinsic (early) failures, which guides the screening through burn-in measures, simply does not work. The fact that improved cleanliness control in the fabrication process does little to reduce early failures also suggests that local thinning due to contamination is not the root cause. In this paper, we propose a new lucky defect model where bulk defects in the gate oxide, introduced during growth, are responsible for the early failures. We argue that a local increase in leakage current via trap-assisted-tunneling (TAT) leads to early oxide breakdown. This argument is supported with oxide breakdown observations in SiC/SiO2 DMOSFETs, as well as simulations that examine various defect distributions and their impact on the resultant early failure distributions.
Citation
IEEE Transactions on Electron Devices
Pub Type
Journals
Keywords
SiC, power MOSFET, reliability, DMOSFET, TDDB, early failures, burn-in
Chbili, Z.
, Matsuda, A.
, Chbili, J.
, Ryan, J.
, Campbell, J.
, Lahbabi, M.
, Ioannou, D.
and Cheung, K.
(2016),
Modeling early breakdown failures of gate oxide in SiC power MOSFETs, IEEE Transactions on Electron Devices
(Accessed October 7, 2025)