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Metrology for the next generation of semiconductor devices

Published

Author(s)

Ndubuisi G. Orji, Mustafa Badaroglu, Bryan M. Barnes, Carlos Beitia, Benjamin D. Bunday, Umberto Celano, Regis J. Kline, Mark Neisser, Yaw S. Obeng, Andras Vladar

Abstract

The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.
Citation
Nature Electronics
Volume
1
Issue
10

Keywords

nanometre scale devices, gate all around, 3DVLSI, SEM, AFM, CD-SAX, Scatterometry, TEM

Citation

Orji, N. , Badaroglu, M. , Barnes, B. , Beitia, C. , Bunday, B. , Celano, U. , Kline, R. , Neisser, M. , Obeng, Y. and Vladar, A. (2018), Metrology for the next generation of semiconductor devices, Nature Electronics, [online], https://doi.org/10.1038/s41928-018-0150-9 (Accessed August 13, 2022)
Created October 12, 2018, Updated January 27, 2020