NOTICE: Due to a lapse in annual appropriations, most of this website is not being updated. Learn more.
Form submissions will still be accepted but will not receive responses at this time. Sections of this site for programs using non-appropriated funds (such as NVLAP) or those that are excepted from the shutdown (such as CHIPS and NVD) will continue to be updated.
An official website of the United States government
Here’s how you know
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
Secure .gov websites use HTTPS
A lock (
) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.
Victor H. Vartanian, Richard A. Allen, Klaus Humler, Steve Olsen, Brian Sapp, Larry Smith
Abstract
This chapter will focus on the metrology steps to support 2.5D and 3D reference flows employing via-mid copper through-silicon via (TSV) processing, wafer thinning, and backside processing using a handle wafer and chip-to-chip bonding. Reference flows that use via formation after thinning or wafer-to-wafer 3D integration will not be addressed.
Vartanian, V.
, Allen, R.
, Humler, K.
, Olsen, S.
, Sapp, B.
and Smith, L.
(2014),
Metrology Needs for 2.5D/3D Interconnect, Handbook of 3D Integration: Volume 3, Wiley, Malden, MA, [online], https://doi.org/10.1002/9783527670109.ch29
(Accessed October 2, 2025)