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Metrology Needs for 2.5D/3D Interconnect



Victor H. Vartanian, Richard A. Allen, Klaus Humler, Steve Olsen, Brian Sapp, Larry Smith


This chapter will focus on the metrology steps to support 2.5D and 3D reference flows employing via-mid copper through-silicon via (TSV) processing, wafer thinning, and backside processing using a handle wafer and chip-to-chip bonding. Reference flows that use via formation after thinning or wafer-to-wafer 3D integration will not be addressed.
Handbook of 3D Integration: Volume 3
Publisher Info
Wiley, Malden, MA


Through silicon via (TSV), Three dimensional stacked integrated circuits (3DS-IC), metrology, interferometry, bond void


Vartanian, V. , Allen, R. , Humler, K. , Olsen, S. , Sapp, B. and Smith, L. (2014), Metrology Needs for 2.5D/3D Interconnect, Handbook of 3D Integration: Volume 3, Wiley, Malden, MA, [online], (Accessed April 14, 2024)
Created June 19, 2014, Updated October 12, 2021