Smee, S.
, Gaitan, M.
, Joshi, Y.
and Blackburn, D.
(1998),
MEMS-Based Test Structures for IC Technology, Proc., ASME, Anaheim, CA, USA
(Accessed April 27, 2025)
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
Secure .gov websites use HTTPS
A lock (
) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.
MEMS-Based Test Structures for IC Technology
Published
Author(s)
, , ,
Abstract
As Integrated Circuit (IC) device sizes shrink, intrinsic and thermo-mechanical stress in interconnects is an ever increasing reliability concern. Increasing device density leads to more interconnect layers and hence, greater probability of stress related failure through mechanisms such as electromigration, delamination and voids. Current state-of-the-art IC technology uses 5 interconnect layers. According to the 1997 SIA Roadmap, that number is expected to increase to 9 by the year 2012. As a result, methods to measure, model and reduce stresses in interconnects are needed to manufacture reliable, future generation IC's.Proceedings Title
Proc., ASME
Conference Dates
November 15-20, 1998
Conference Location
Anaheim, CA, USA
Pub Type
Conferences
Keywords
circuit, CMOS, MEMS, interconnect, integrated circuit, strain, stress, test structures
Citation
Issues
If you have any questions about this publication or are having problems accessing it, please contact reflib@nist.gov.
Created December 30, 1998, Updated October 12, 2021